Power transistor with terminal trenches in terminal resurf regions

1. A device, comprising:

a semiconductor substrate having a top surface defining a transistor region and a peripheral region laterally surrounding the transistor region;

an n-doped layer under the top surface;

a first trench within the transistor region, the first trench extending from the top surface and partially penetrating the n-doped layer;

a second trench within the peripheral region, the second trench coextending with the first trench;

a first p-doped region adjacent to the top surface and abutting the first trench; and

a second p-doped region adjacent to the top surface and abutting the first trench and the second trench.

2. The device of claim 1 , wherein:

the first p-doped region having a first depth extending from the top surface; and

the second p-doped region having a second depth extending from the top surface and greater than the first depth.

3. The device of claim 1 , wherein:

the first p-doped region having a first doping concentration; and

the second p-doped region having a second doping concentration lower than the first doping concentration.

4. The device of claim 1 , wherein the second p-doped region is interposed between the first p-doped region and the second trench.

5. The device of claim 1 , wherein the second p-doped region laterally surrounds the transistor region.

6. The device of claim 1 , wherein the second p-doped region laterally surrounds the second trench.

7. The device of claim 1 , further comprising:

an n-doped region positioned within the first p-doped region and abutting the first trench.

8. The device of claim 1 , further comprising:

an n-doped region outside the first p-doped region and the peripheral region, the n-doped region positioned below the top surface and above the n-doped layer.

9. The device of claim 1 , further comprising:

an oxide layer above the second trench and demarcating a boundary of the peripheral region, wherein the first p-doped region terminates around the boundary and the second p-doped region extends across the boundary.

10. The device of claim 1 , wherein the second trench includes:

a longitudinal trench parallel to the first trench; and

a traverse trench perpendicular to the first trench, the traverse trench separated from the longitudinal trench, and the traverse trench staggering the longitudinal trench along a corner of the peripheral region.

11. A transistor, comprising:

an n-type drain contact layer;

an n-type drain layer on the n-type drain contact layer;

an oxide layer above the n-type drain layer and circumscribing a transistor region;

a p-type body region within the transistor region and near a top portion of the n-type drain layer;

a p-type terminal region extending from under the oxide layer to an edge of the transistor region, and forming a contiguous junction with the p-type body region;

body trenches within the transistor region and interleaving with the p-type body region; and

terminal trenches outside the transistor region and interleaving with the p-type terminal region.

12. The transistor of claim 11 , wherein:

the p-type body region having a first depth extending from the top portion; and

the p-type terminal region having a second depth extending from the top portion and greater than the first depth.

13. The transistor of claim 11 , wherein:

the p-type body region having a first doping concentration; and

the p-type terminal region having a second doping concentration lower than the first doping concentration.

14. The transistor of claim 11 , further comprising:

an n-type source region positioned within the p-type body region and accessing the body trenches.

15. The transistor of claim 11 , further comprising:

an n-type lightly doped drain (LDD) region outside the p-type body region and interposed between two of the body trenches.

16. The transistor of claim 11 , wherein the terminal trenches includes:

longitudinal trenches parallel to the body trenches; and

traverse trenches perpendicular to the body trenches, the traverse trenches isolated from the longitudinal trenches, and the traverse trenches arrange with the longitudinal trenches a staggering pattern embracing a corner of the transistor region.

17. An integrated circuit, comprising:

an n-type drain contact layer;

an n-type drain layer on the n-type drain contact layer;

an oxide layer above the n-type drain layer and circumscribing transistor regions; and

transistors, each including:

a p-type body region within at least one of the transistor regions and near a top portion of the n-type drain layer;

a p-type terminal region extending from under the oxide layer to an edge of at least one of the transistor regions, and forming a contiguous junction with the p-type body region;

body trenches within at least one of the transistor regions and interleaving with the p-type body region; and

terminal trenches outside at least one of the transistor regions and interleaving with the p-type terminal region.

18. The integrated circuit of claim 17 , wherein:

the p-type body region having a first depth extending from the top portion; and

the p-type terminal region having a second depth extending from the top portion and greater than the first depth.

19. The integrated circuit of claim 17 , wherein:

the p-type body region having a first doping concentration; and

the p-type terminal region having a second doping concentration lower than the first doping concentration.

20. The integrated circuit of claim 17 , wherein the terminal trenches includes:

longitudinal trenches parallel to the body trenches; and

traverse trenches perpendicular to the body trenches, the traverse trenches isolated from the longitudinal trenches, and the traverse trenches arrange with the longitudinal trenches a staggering pattern embracing a corner of each of the transistor regions.