Architecture to scale finite-state machines across integrated circuits using a digital bus

1. A power supply management system, the system comprising:

a plurality of power supplies, wherein a power supply provides a supply voltage rail to a voltage domain of the system;

a plurality of power supply voltage sequencer devices, respectively electrically coupled to multiple power supplies of the plurality of power supplies, wherein each individual voltage sequencer device is configured to activate the multiple power supplies in a specified device state sequence; and

a bus electrically coupled to the plurality of power supply voltage sequencer devices, wherein one or more voltage sequencer devices are configured to communicate a device state via the bus to progress activation of the plurality of power supplies.

2. The system of claim 1 , wherein the plurality of power supply voltage sequencer devices includes a master device and one or more slave devices, wherein the plurality of power supply voltage sequencer devices sequence through multiple device states to activate the plurality of power supply devices, and wherein the master device is configured to broadcast a device state to the one or more slave devices via the bus to place all of the voltage sequencer devices in the same device state.

3. The system of claim 2 , wherein the one more slave devices are configured to send fault status information to the master device, and the master device broadcasts a device state to the one or more slave devices according to the received fault status information.

4. The system of claim 1 , wherein each of the power supply voltage sequencer devices includes a finite state machine that sequences the power supply voltage sequencer device through multiple device states to activate the multiple power supply devices to which it is electrically coupled, wherein only one voltage sequencer device sequences through device states at a time and communicates status of the sequencing to the other power supply voltage sequencer devices via the bus.

5. The system of claim 4 , wherein a power supply voltage sequencer device broadcasts fault status information to the other the power supply voltage sequencer devices, and the power supply voltage sequencer devices change device state according to received fault status information.

6. The system of claim 1 , wherein each of the power supply voltage sequencer devices includes a finite state machine, wherein the finite state machine is implemented as logic circuitry.

7. The system of claim 1 , including a graphical user interface (GUI) and a processor, wherein each of the power supply voltage sequencer devices includes a finite state machine, wherein the processor is configured to program device states of the finite state machine in the plurality of power supply voltage sequencer devices using information received using the GUI.

8. The system of claim 7 , wherein the processor is configured to program power supply operating properties in the plurality of power supply voltage sequencer devices using information received using the GUI.

9. The system of claim 7 , wherein the processor is configured to receive operating status information from the plurality of power supply voltage sequencer devices and display operating status of power supply voltage rails using the GUI.

10. The system of claim 1 , wherein the bus is an inter-integrated circuit (I 2 C) bus.

11. An integrated circuit to control power supply activation, the integrated circuit comprising:

control circuitry configured to activate and deactivate multiple power supplies;

a bus interface to a multi-line inter-chip cascade bus; and

logic circuitry configurable, using a message received via the bus interface, as a finite state machine to generate control signals to sequentially activate and deactivate the multiple power supplies.

12. The integrated circuit of claim 11 , wherein the logic circuitry is configured to communicate state information of the finite state machine via the bus interface.

13. The integrated circuit of claim 11 , including monitoring circuitry configured to monitor the operating status of the multiple power supplies and communicate operating status information via the bus interface.

14. The integrated circuit of claim 11 , wherein the bus interface is an inter-integrated circuit (I 2 C) bus interface.

15. A non-transitory computer readable storage medium including instructions that, when performed by processing circuitry of a computing device, cause the computing device to perform acts comprising:

implementing a graphical user interface (GUI) on the computing device;

receiving power supply voltage sequencer information via the GUI; and

configuring, using the power supply voltage sequencer information, a plurality of power supply voltage sequencer devices to coordinate activation of a plurality of power supplies in a specified sequence, wherein a power supply provides a supply voltage rail to a voltage domain of an electronic system, and wherein a power supply voltage sequencer controls activation of more than one power supply.

16. The non-transitory computer readable storage medium of claim 15 , including instructions that cause the processing circuitry to:

configure a state machine in each of the power supply voltage sequencer devices, wherein a power supply voltage sequencer device sequentially activates and deactivates power supplies to which it is connected according to the configured state machine; and

configure a power supply voltage sequencer device as a master device and one or more other power supply voltage sequencer devices as slave devices, wherein the master device is configured to broadcast a device state to the one or more slave devices to place all of the voltage sequencer devices in the same device state.

17. The non-transitory computer readable storage medium of claim 15 , including instructions that cause the processing circuitry to: configure a state machine in each of the power supply voltage sequencer devices, wherein a power supply voltage sequencer device sequentially activates and deactivates power supplies to which it is connected according to the configured state machine, wherein only one voltage sequencer device sequences through device states at a time and communicates status of the sequencing to the other power supply voltage sequencer devices.

18. The non-transitory computer readable storage medium of claim 15 , including instructions that cause the processing circuitry to receive power supply operating properties via the GUI and program the plurality of power supply voltage sequencer devices using the received power supply operating properties.

19. The non-transitory computer readable storage medium of claim 15 , including instructions that cause the processing circuitry to receive operating status information from the plurality of power supply voltage sequencer devices and display operating status of power supply voltage rails using the GUI.

20. The non-transitory computer readable storage medium of claim 15 , including instructions that cause the processing circuitry to send configuration information to a power supply voltage sequencer device and receive operating status information from the power supply voltage sequencer device according to an inter-integrated circuit (I 2 C) bus protocol.