IP Library Granted Patent US 10,195,716
Granted Patent B2
US 10,195,716 · App. 15/429,542 · Granted Feb 5, 2019

Dresser, method of manufacturing dresser, and method of manufacturing semiconductor device

Inventors: Takahiko Kawasaki (Aichi, JP); Yukiteru Matsui (Aichi, JP); Akifumi Gawase (Mie, JP)
Assignee: TOSHIBA MEMORY CORPORATION
B24B53/017H01L21/30625
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Quick Facts
Patent No.
US 10,195,716
App. No.
15/429,542
Granted
Feb 5, 2019
Kind
B2
Abstract

According to one embodiment, a dresser includes a base metal plate, and a plurality of chip portions that are provided on the base metal plate. Each chip portion includes a Si substrate having a projection at an upper portion thereof and a diamond layer provided on the projection of the Si substrate.

Claims (40)

1. A dresser comprising:

a base metal plate; and

a plurality of chip portions that are provided on the base metal plate, each of the chip portions including:

a Si substrate having a projection at an upper portion of the Si substrate, and

a diamond layer provided on the projection of the Si substrate.

2. The dresser according to claim 1 ,

wherein each Si substrate has a plane orientation of (111).

3. The dresser according to claim 1 ,

wherein the base metal plate partially protrudes at respective joining portions between the base metal plate and each chip portion.

4. The dresser according to claim 1 ,

wherein a shape of each projection is a conical shape.

5. The dresser according to claim 1 ,

wherein at least one chip portion of the plurality of chip portions includes a plurality of projections at an upper portion of the Si substrate of the chip portion arranged to form a honeycomb structure.

6. A method of manufacturing a dresser, comprising:

providing a Si substrate having a plurality of projections on a surface thereof;

preparing a chip portion by cutting the Si substrate into individual pieces, one piece constituting the chip portion, the chip portion including one or more projections of the plurality of projections;

forming a diamond layer on the one or more projections of the chip portion; and

providing the chip portion on a base metal plate.

7. The method of manufacturing the dresser according to claim 6 ,

wherein the Si substrate is cut into the individual pieces to prepare a plurality of the chip portions, and after the diamond layer is formed on the projections of the plurality of chip portions, the plurality of chip portions are provided on the base metal plate.

8. The method of manufacturing the dresser according to claim 6 ,

wherein the Si substrate has a plane orientation of (111).

9. The method of manufacturing the dresser according to claim 6 ,

wherein the Si substrate is a Si wafer.

10. The method of manufacturing the dresser according claim 6 ,

wherein a shape of each projection is a conical shape.

11. The method of manufacturing the dresser according claim 6 ,

wherein the chip portion is provided on a chip holding base that is formed on the base metal plate.

12. The method of manufacturing the dresser according claim 6 ,

wherein the surface of the Si substrate is etched to form the plurality of projections simultaneously.

13. The method of manufacturing the dresser according to claim 6 ,

wherein the one or more projections of the chip portion are arranged to form a honeycomb structure.

14. A method of manufacturing a semiconductor device, comprising:

providing a semiconductor wafer;

dressing a polishing pad using a dresser, the dresser comprising a base metal plate and chip portions obtained by cutting a Si substrate, at least one chip portion having one or more projections on a surface thereof, the one or more projections covered with a diamond layer, the individual chip portions being provided on the base metal plate; and

polishing the semiconductor wafer using the dressed polishing pad.

15. A method of manufacturing a semiconductor device according to claim 14 , wherein the at least one chip portion includes a portion of the Si substrate having a plane orientation of (111).

16. A method of manufacturing a semiconductor device according to claim 14 , wherein the base metal plate partially protrudes at respective joining portions between the base metal plate and each chip portion.

17. A method of manufacturing a semiconductor device according to claim 14 , wherein a shape of the projection is a conical shape.

18. A method of manufacturing a semiconductor device according to claim 14 , wherein the one or more projections of the at least one chip portion are arranged to form a honeycomb structure.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043063/0178 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 10, 2017
From: KAWASAKI, TAKAHIKO; MATSUI, YUKITERU; GAWASE, AKIFUMI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 041224/0535 →
Priority Claims (1)
JP 2016-164015 · Aug 24, 2016 · national
Continuity (1)
Related Publication 20180056482A1 · Mar 1, 2018