System and method for providing a back door communication path between channels on dual-channel DIMMs

1. A dual-channel Dual In-Line Memory Module (DIMM), comprising:

a first bank of Dynamic Random Access Memory (DRAM) devices configured to provide a first memory transaction on the first memory channel of a memory controller of an information handling system;

a second bank of DRAM devices configured to provide a second memory transaction on the second memory channel of the memory controller; and

a plurality of back door communication paths, each back door communication path being between a first data bit of the first bank of DRAM devices and a second data bit of the second bank of DRAM devices, the first data bit corresponding to a particular address on the first memory channel and the second data bit corresponding to the particular address on the second memory channel.

2. The dual-channel DIMM of claim 1 , wherein the dual-channel DIMM is configured to provide the first memory transaction on the second memory channel in response to determining that the first memory channel has failed to provide the first memory transaction, wherein data associated with the first memory transaction is communicated between the first bank of DRAM devices and the second bank of DRAM devices to the second memory channel via the plurality of back door communication paths.

3. The dual-channel DIMM of claim 2 , further comprising:

a Register Control Device (RCD) configured in a normal operating mode to:

receive first command and address information associated with the first transaction on the first memory channel,

provide the first command and address information to the first bank of DRAM devices

receive second command and address information associated with the second on the second memory channel; and

provide the second command and address information to the second bank of DRAM devices.

4. The dual-channel DIMM of claim 3 , wherein the RCD is further configured to provide the first command and address information to the second bank of DRAM devices in further response to determining that the first memory channel has failed to provide the first memory transaction.

5. The dual-channel DIMM of claim 1 , wherein each DRAM device of the first and second banks of DRAM devices is configured as a two-port device, each DRAM device having a first port and a second port.

6. The dual-channel DIMM of claim 5 , wherein, in providing the plurality of back door communication paths, the dual-channel DIMM is configured such that each first port of each DRAM device of the first bank of DRAM devices is connected to a first port of a corresponding DRAM device of the second bank of DRAM devices.

7. The dual-channel DIMM of claim 6 , wherein:

the first bank of DRAM devices is configured such that each second port of each DRAM device of the first bank of DRAM devices provides memory transactions to the first memory channel; and

the second bank of DRAM devices is configured such that each second port of each DRAM device of the second bank of DRAM devices provides memory transactions to the second memory channel.

8. The dual-channel DIMM of claim 7 , wherein each DRAM device of the first and second banks of DRAM devices is further configured to provide a pass-through mode, wherein, in the pass-through mode, first data presented on each first port is passed through each DRAM device to each second port, and second data presented on each second port is passed through each DRAM device to each first port, wherein the pass-through mode is in response to a failure on one of the first and second memory channels.

9. The dual-channel DIMM of claim 5 , wherein each DRAM device of the first and second banks of DRAM devices is further configured to provide four-bits of data.

10. The dual-channel DIMM of claim 9 , wherein the dual-channel DIMM comprises one of an unbuffered DIMM, a registered DIMM, a load reduced DIMM, and a storage class memory DIMM.

11. A method of providing a dual-channel Dual In-Line Memory Module (DIMM), the method comprising:

providing a first bank of Dynamic Random Access Memory (DRAM) devices of the dual-channel DIMM, the first bank of DRAM devices to conduct a first memory transaction on a first memory channel of a memory controller of an information handling system;

providing a second bank of DRAM devices of the dual-channel DIMM, the second bank of DRAM devices to conduct a second memory transaction on a second memory channel of the memory controller; and

providing a plurality of back door communication paths, each back door communication path being between a first data bit of the first bank of DRAM devices and a second data bit of the second bank of DRAM devices, the first data bit corresponding to a particular address on the first memory channel and the second data bit corresponding to the particular address on the second memory channel.

12. The method of claim 11 , wherein, in response to determining that the first memory channel has failed to provide the first memory transaction, the method further comprises:

configuring the dual-channel DIMM to conduct the first memory transaction on the second memory channel; and

communicating data associated with the first memory transaction between the first bank of DRAM devices and the second bank of DRAM devices to the second memory channel via the plurality of back door communication paths.

13. The method of claim 12 , further comprising:

providing a Register Control Device (RCD) of the dual-channel DIMM;

receiving, by the RCD, first command and address information associated with the first transaction on the first memory channel in a normal operating mode;

providing, by the RCD, the first command and address information to the first bank of DRAM devices in the normal operating mode;

receiving, by the RCD, second command and address information associated with the second transaction on the second memory channel in the normal operating mode; and

providing, by the RCD, the second command and address information to the second bank of DRAM devices in the normal operating mode.

14. The method of claim 13 , further comprising:

providing, by the RCD, the first command and address information to the second bank of DRAM devices in further response to determining that the first memory channel has failed to provide the first memory transaction.

15. The method of claim 11 , wherein each DRAM device of the first and second banks of DRAM devices is configured as a two-port device, each DRAM device having a first port and a second port.

16. The method of claim 15 , wherein, in providing the plurality of back door communication paths, the method further comprises:

connecting each first port of each DRAM device of the first bank of DRAM devices to a first port of a corresponding DRAM device of the second bank of DRAM devices.

17. The method of claim 16 , further comprising:

conducting the first memory transaction via each second port of each DRAM device of the first bank of DRAM devices; and

conducting the second memory transaction via each second port of each DRAM device of the second bank of DRAM devices.

18. The method of claim 17 , further comprising:

configuring each DRAM device of the first and second banks of DRAM devices to provide a pass-through mode, wherein, in the pass-through mode, first data presented on each first port is passed through each DRAM device to each second port, and second data presented on each second port is passed through each DRAM device to each first port, wherein the pass-through mode is in response to a failure on one of the first and second memory channels.

19. The method of claim 15 , wherein each DRAM device of the first and second banks of DRAM devices is further configured to provide four-bits of data.

20. An information handling system, comprising;

a memory controller for dual-channel Dual In-Line Memory Module (DIMM), the memory controller configured to provide memory transactions on a first memory channel and a second memory channel; and

a dual-channel DIMM comprising:

a first bank of Dynamic Random Access Memory (DRAM) devices configured to provide a first memory transaction on the first memory channel;

a second bank of DRAM devices configured to provide a second memory transaction on the second memory channel; and

a plurality of back door communication paths, each back door communication path being between a first data bit of the first bank of DRAM devices and a second data bit of the second bank of DRAM devices, the first data bit corresponding to a particular address on the first memory channel and the second data bit corresponding to the particular address on the second memory channel.