IP Library Granted Patent US 10,437,646
Granted Patent B2
US 10,437,646 · App. 15/430,657 · Granted Oct 8, 2019

Automatic detection of optimal compute unit partitioning

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Quick Facts
Patent No.
US 10,437,646
App. No.
15/430,657
Granted
Oct 8, 2019
Kind
B2
Abstract

A system, method, and computer-readable medium are disclosed for performing an automatic partition optimization operation on a processor, comprising: monitoring compute unit usage of the processor over time; determining whether an application executing on the processor comprises a lightly threaded application or a heavily threaded application; and, automatically adjusting compute unit partitioning of the processor based upon whether the application executing on the processor comprises the lightly threaded application or the heavily threaded application.

Claims (51)

1. A computer-implementable method for performing an automatic partition optimization operation on a processor, comprising:

monitoring compute unit usage of the processor over time;

determining whether an application executing on the processor comprises a lightly threaded application or a heavily threaded application, a lightly threaded application corresponding to a percentage of processor usage below 30 percent, a heavily threaded application corresponding to the percentage of processor usage above 50 percent;

determining whether the application executing on the processor results in a mixed use compute usage;

providing programmable thresholds for use when adjusting compute unit partitioning, the programmable thresholds providing a tenability function and a hysteresis function when adjusting compute partitioning of processor; and,

automatically adjusting compute unit partitioning of the processor based upon whether the application executing on the processor comprises the lightly threaded application or the heavily threaded application.

2. The method of claim 1 , wherein:

for lighter threaded compute unit usage, the compute units are automatically partitioned to maximize performance by eliminating conflicts due to resource sharing.

3. The method of claim 1 , wherein:

for heavily threaded compute unit usage, the compute units are partitioned to maximize symmetric multi-processing capabilities.

4. The method of claim 1 , wherein:

the determining whether an application executing on the processor comprises a lightly threaded application or a heavily threaded application comprises identifying a percentage of processor usage.

5. The method of claim 4 , wherein:

the percentage of processor usage is analyzed across a plurality of regular time intervals.

6. The method of claim 1 , further comprising:

querying a basic input output system (BIOS) to determine a currently configured compute unit partitioning scheme.

7. A system comprising:

a processor;

a data bus coupled to the processor; and

a non-transitory, computer-readable storage medium embodying computer program code, the non-transitory, computer-readable storage medium being coupled to the data bus, the computer program code interacting with a plurality of computer operations and comprising instructions executable by the processor and configured for:

monitoring compute unit usage of the processor over time;

determining whether an application executing on the processor comprises a lightly threaded application or a heavily threaded application, a lightly threaded application corresponding to a percentage of processor usage below 30 percent, a heavily threaded application corresponding to the percentage of processor usage above 50 percent;

determining whether the application executing on the processor results in a mixed use compute usage;

providing programmable thresholds for use when adjusting compute unit partitioning, the programmable thresholds providing a tenability function and a hysteresis function when adjusting compute partitioning of processor; and,

automatically adjusting compute unit partitioning of the processor based upon whether the application executing on the processor comprises the lightly threaded application or the heavily threaded application.

8. The system of claim 7 , wherein:

for lighter threaded compute unit usage, the compute units are automatically partitioned to maximize performance by eliminating conflicts due to resource sharing.

9. The system of claim 7 , wherein:

for heavily threaded compute unit usage, the compute units are partitioned to maximize symmetric multi-processing capabilities.

10. The system of claim 7 , wherein:

the determining whether an application executing on the processor comprises a lightly threaded application or a heavily threaded application comprises identifying a percentage of processor usage.

11. The system of claim 10 , wherein:

the percentage of processor usage is analyzed across a plurality of regular time intervals.

12. The system of claim 7 , wherein the instructions are further configured for:

querying a basic input output system (BIOS) to determine a currently configured compute unit partitioning scheme.

13. A non-transitory, computer-readable storage medium embodying computer program code, the computer program code comprising computer executable instructions configured for:

monitoring compute unit usage of a processor over time;

determining whether an application executing on the processor comprises a lightly threaded application or a heavily threaded application, a lightly threaded application corresponding to a percentage of processor usage below 30 percent, a heavily threaded application corresponding to the percentage of processor usage above 50 percent;

determining whether the application executing on the processor results in a mixed use compute usage;

providing programmable thresholds for use when adjusting compute unit partitioning, the programmable thresholds providing a tenability function and a hysteresis function when adjusting compute partitioning of processor; and,

automatically adjusting compute unit partitioning of the processor based upon whether the application executing on the processor comprises the lightly threaded application or the heavily threaded application.

14. The non-transitory, computer-readable storage medium of claim 13 , wherein:

for lighter threaded compute unit usage, the compute units are automatically partitioned to maximize performance by eliminating conflicts due to resource sharing.

15. The non-transitory, computer-readable storage medium of claim 13 , wherein:

for heavily threaded compute unit usage, the compute units are partitioned to maximize symmetric multi-processing capabilities.

16. The non-transitory, computer-readable storage medium of claim 13 , wherein:

the determining whether an application executing on the processor comprises a lightly threaded application or a heavily threaded application comprises identifying a percentage of processor usage.

17. The non-transitory, computer-readable storage medium of claim 16 , wherein:

the percentage of processor usage is analyzed across a plurality of regular time intervals.

18. The non-transitory, computer-readable storage medium of claim 13 , wherein the instructions are further configured for:

querying a basic input output system (BIOS) to determine a currently configured compute unit partitioning scheme.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (042769/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 059803/0802 →
RELEASE OF SECURITY INTEREST AT REEL 042768 FRAME 0585 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058297/0536 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY INTEREST (CREDIT) Recorded Jun 12, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 042768/0585 →
PATENT SECURITY INTEREST (NOTES) Recorded Jun 12, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 042769/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 13, 2017
From: SHOWS, THOMAS ALEXANDER; MORTON, CHARLES G.
To: DELL PRODUCTS L.P.
Reel/Frame 041235/0093 →