IP Library Granted Patent US 10,303,560
Granted Patent B2
US 10,303,560 · App. 15/431,932 · Granted May 28, 2019

Systems and methods for eliminating write-hole problems on parity-based storage resources during an unexpected power loss

Inventors: Chandrashekar Nelogal (Round Rock, TX); Anand Nunna (Round Rock, TX)
Assignee: Dell Products L.P.
G06F11/1469G06F11/108G06F12/0804G06F2201/84G06F2212/1032G06F2212/60
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Quick Facts
Patent No.
US 10,303,560
App. No.
15/431,932
Granted
May 28, 2019
Kind
B2
Abstract

In accordance with embodiments of the present disclosure, a method may include, during a cache flush of data of a cache entry from a non-volatile memory to a storage resource, wherein the non-volatile memory is integral to a persistent write-back cache and storing the data in response to a power event associated with the write-back cache: (a) calculating a calculated parity value by undertaking a read-modify-write operation with respect to the storage resource; and (b) storing the calculated parity value and a target address of the storage resource associated with the calculated parity value in a parity journal.

Claims (48)

1. A method comprising, during a cache flush of data of a cache entry from a non-volatile memory to a storage resource, wherein the non-volatile memory is integral to a persistent write-back cache and is configured to store the data in response to a power event associated with the write-back cache:

determining whether a parity journal embodied in persistent memory includes an entry having a calculated parity for data existing in the persistent write-back cache generated during a previous boot session of an information handling system comprising the write-back cache;

determining whether the parity journal includes an entry indicating a write operation uncompleted during the previous boot session;

in response to the parity journal including the entry having the calculated parity, issuing write requests to the storage resource for the data existing in the persistent write-back cache and the calculated parity; and

in response to the parity journal indicating a write operation uncompleted during the previous boot session, issuing a write request to the storage resource for data existing in the persistent write-back cache associated with the write operation.

2. The method of claim 1 , further comprising, in response to a cache entry existing in the persistent write-back cache for which the parity journal includes no corresponding entry having a calculated parity:

calculating the calculated parity by undertaking a read-modify-write operation with respect to one or more storage resources comprising the storage resource for the data existing in the persistent write-back cache; and

issuing write requests to the storage resource for the data of the cache entry and for the calculated parity associated with the data.

3. The method of claim 1 , further comprising, in response to an acknowledgement of completion of the write request for data the calculated parity, deleting the entry of the parity journal associated with the calculated parity.

4. The method of claim 1 , further comprising, in response to an acknowledgement of completion of the write request for data of the write operation uncompleted during the previous boot session, deleting the entry of the write operation uncompleted during the previous boot session.

5. The method of claim 1 , wherein the parity journal is embodied in non-volatile memory.

6. A system comprising:

a persistent write-back cache comprising:

a volatile memory;

a non-volatile memory for backing up data stored within the volatile memory; and

a processor configured to, during a cache flush of data of a cache entry from the non-volatile memory to a storage resource in response to a power event associated with the write-back cache:

determine whether a parity journal embodied in persistent memory includes an entry having a calculated parity for data existing in the persistent write-back cache during a previous boot session of the system;

determine whether the parity journal includes an entry indicating a write operation uncompleted during the previous boot session;

in response to the parity journal including the entry having the calculated parity, issue write requests to the storage resource for the data existing in the persistent write-back cache and the calculated parity; and

in response to the parity journal indicating the write operation uncompleted during the previous boot session, issue a write request to the storage resource for data existing in the persistent write-back cache associated with the write operation.

7. The system of claim 6 , the processor further configured to, in response to a cache entry existing in the persistent write-back cache for which the parity journal includes no corresponding entry having a calculated parity:

calculate the calculated parity by undertaking a read-modify-write operation with respect to one or more storage resources comprising the storage resource for the data existing in the persistent write-back cache; and

issue write requests to the storage resource for the data of the cache entry and for the calculated parity associated with the data.

8. The system of claim 6 , the processor further configured to, in response to an acknowledgement of completion of the write request for the calculated parity, delete the entry of the parity journal associated with the calculated parity.

9. The system of claim 6 , the processor further configured to, in response to an acknowledgement of completion of the write request for data of the write operation uncompleted during the previous boot session, delete the entry of the write operation.

10. The system of claim 6 , wherein the processor is integral to a storage controller for executing hardware-based storage redundancy.

11. The system of claim 6 , wherein the processor is configured to execute software-based storage redundancy.

12. The system of claim 6 , wherein the parity journal is embodied in non-volatile memory.

13. A method comprising, during a cache flush of data of a cache entry from a non-volatile memory to a storage resource, wherein the non-volatile memory is integral to a persistent write-back cache and is configured to store the data in response to a power event associated with the write-back cache:

calculating a calculated parity value by undertaking a read-modify-write operation with respect to the storage resource; and

storing the calculated parity value and a target address of the storage resource associated with the calculated parity value in a parity journal.

14. The method of claim 13 , further comprising issuing write requests to the storage resource for the data of the cache entry and for the calculated parity value associated with the data.

15. The method of claim 14 , further comprising, in response to an acknowledgement of completion of the write request for the calculated parity value, deleting the entry of the parity journal associated with the calculated parity from the parity journal.

16. The method of claim 13 , further comprising storing a second target address of the storage resource, the second target address associated with the write data.

17. The method of claim 16 , further comprising, in response to an acknowledgement of completion of the write request for the write data, deleting the entry of the parity journal associated with the second target address from the parity journal.

18. The method of claim 13 , wherein the parity journal is embodied in non-volatile memory.

19. A system comprising:

a persistent write-back cache comprising:

a volatile memory;

a non-volatile memory for backing up data stored within the volatile memory; and

a processor configured to, during a cache flush of data of a cache entry from the non-volatile memory to a storage resource in response to a power event associated with the write-back cache:

calculate a calculated parity value by undertaking a read-modify-write operation with respect to the storage resource; and

store the calculated parity value and a target address of the storage resource associated with the calculated parity value in a parity journal.

20. The system of claim 19 , the processor further configured to issue write requests to the storage resource for the data of the cache entry and for the calculated parity value associated with the data.

21. The system of claim 20 , the processor further configured to, in response to an acknowledgement of completion of the write request for the calculated parity value, delete the entry of the parity journal associated with the calculated parity value from the parity journal.

22. The system of claim 19 , the processor further configured to store a second target address of the storage resource, the second target address associated with the write data.

23. The system of claim 22 , the processor further configured to, in response to an acknowledgement of completion of the write request for the write data, delete the entry of the parity journal associated with the second target address from the parity journal.

24. The system of claim 19 , wherein the parity journal is embodied in non-volatile memory.

Assignments (8)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (053546/0001) Recorded Jun 23, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL MARKETING L.P. (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO CREDANT TECHNOLOGIES, INC.); DELL INTERNATIONAL L.L.C.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO FORCE10 NETWORKS, INC. AND WYSE TECHNOLOGY L.L.C.); EMC IP HOLDING COMPANY LLC
Reel/Frame 071642/0001 →
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL/FRAME (042769/0001) Recorded Apr 26, 2022
From: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS NOTES COLLATERAL AGENT
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC (ON BEHALF OF ITSELF AND AS SUCCESSOR-IN-INTEREST TO MOZY, INC.); DELL MARKETING CORPORATION (SUCCESSOR-IN-INTEREST TO WYSE TECHNOLOGY L.L.C.)
Reel/Frame 059803/0802 →
RELEASE OF SECURITY INTEREST AT REEL 042768 FRAME 0585 Recorded Nov 2, 2021
From: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH
To: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
Reel/Frame 058297/0536 →
SECURITY AGREEMENT Recorded Apr 22, 2020
From: CREDANT TECHNOLOGIES INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 053546/0001 →
SECURITY AGREEMENT Recorded Mar 21, 2019
From: CREDANT TECHNOLOGIES, INC.; DELL INTERNATIONAL L.L.C.; DELL MARKETING L.P.; DELL PRODUCTS L.P.; DELL USA L.P.; EMC CORPORATION; FORCE10 NETWORKS, INC.; WYSE TECHNOLOGY L.L.C.; EMC IP HOLDING COMPANY LLC
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A.
Reel/Frame 049452/0223 →
PATENT SECURITY INTEREST (CREDIT) Recorded Jun 12, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: CREDIT SUISSE AG, CAYMAN ISLANDS BRANCH, AS COLLATERAL AGENT
Reel/Frame 042768/0585 →
PATENT SECURITY INTEREST (NOTES) Recorded Jun 12, 2017
From: DELL PRODUCTS L.P.; EMC CORPORATION; EMC IP HOLDING COMPANY LLC; MOZY, INC.; WYSE TECHNOLOGY L.L.C.
To: THE BANK OF NEW YORK MELLON TRUST COMPANY, N.A., AS COLLATERAL AGENT
Reel/Frame 042769/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 14, 2017
From: NELOGAL, CHANDRASHEKAR; NUNNA, ANAND
To: DELL PRODUCTS L.P.
Reel/Frame 041249/0639 →
Continuity (1)
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