Performance optimization in soft decoding of error correcting codes

1. A method for decoding a first codeword, comprising:

obtaining a first message comprising reliability information corresponding to each bit in the first codeword, wherein the first codeword comprises a first constituent codeword of a turbo product code (TPC) codeword;

determining a plurality of least reliable bits in the first codeword based on the reliability information, wherein a number of the plurality of least reliable bits is equal to a first parameter “L” of a Chase decoder, wherein the first parameter “L” represents “L” possible error locations in the first codeword;

generating, based on the Chase decoder, a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first, wherein a number of flipped bits in each of the plurality of flipped messages is limited to a second parameter “S” of the Chase decoder, wherein the second parameter “S” is smaller than the first parameter “L” and represents a maximum number of allowable bit-flips out of the “L” possible error locations; and

decoding one or more of the plurality of flipped messages using at least the Chase decoder to generate one or more candidate codewords.

2. The method of claim 1 , further comprising:

selecting a decoded message from the one or more candidate codewords based on a Euclidian distance of the one or more candidate codewords from the first codeword.

3. The method of claim 1 , wherein the second parameter is based on a latency simulation of the Chase decoder.

4. The method of claim 1 , wherein decoding the plurality of flipped messages comprises decoding each of the plurality of flipped messages using the Chase decoder.

5. The method of claim 1 , wherein the first codeword is a Bose-Chaudhuri-Hocquenghem (BCH) codeword.

6. The method of claim 5 , wherein the TPC codeword comprises a plurality of constituent codewords, the method further comprising:

decoding the first constituent codeword of the TPC codeword in a set of decoding iterations by using the first parameter “L” and the second parameter “S;” and

decoding a second constituent codeword of the TPC codeword in a subsequent set of decoding iterations by at least increasing the first parameter “L” to a third parameter “L” and increasing the second parameter “S” to a fourth parameter “S”.

7. The method of claim 6 , wherein a value of the fourth parameter is different from a value of the second parameter.

8. An apparatus for decoding a first codeword, comprising:

a memory;

at least one processor coupled to the memory, the at least one processor configured to:

obtain a first message comprising reliability information corresponding to each bit in the first codeword, wherein the first codeword comprises a first constituent codeword of a turbo product code (TPC) codeword;

determine a plurality of least reliable bits in the first codeword codeword based on the reliability information, wherein a number of the plurality of least reliable bits is equal to a first parameter “L” of a Chase decoder, wherein the first parameter “L” represents “L” possible error locations in the first codeword;

generate, based on the Chase decoder, a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword, wherein a number of flipped bits in each of the plurality of flipped messages limited to a second parameter “S” of the Chase decoder, wherein the second parameter “S” is smaller than the first parameter “L” and represents a maximum number of allowable bit-flips out of the “L” possible error locations; and

decode one or more of the plurality of flipped messages using at least the Chase decoder to generate one or more candidate codewords.

9. The apparatus of claim 8 , wherein the at least one processor is further configured to:

select a decoded message from the one or more candidate codewords based on a Euclidian distance of the one or more candidate codewords from the first codeword.

10. The apparatus of claim 8 , wherein the second parameter is based on a latency simulation of the Chase decoder.

11. The apparatus of claim 8 , wherein the at least one processor is further configured to decode each of the plurality of flipped messages using the Chase decoder.

12. The apparatus of claim 8 , wherein the first codeword is a Bose-Chaudhuri-Hocquenghem (BCH) codeword.

13. The apparatus of claim 12 , wherein the TPC codeword comprises a plurality of constituent codewords, wherein the at least one processor is further configured to:

decode the first constituent codeword of the TPC codeword in a set of decoding iterations by using the first parameter “L” and the second parameter “S;” and

decode a second constituent codeword of the TPC codeword in a subsequent set of decoding iterations by at least increasing the first parameter “L” to a third parameter “L” and increasing the second parameter “S” to a fourth parameter “S”.

14. The apparatus of claim 13 , wherein a value of the fourth parameter is different from a value of the second parameter.

15. A non-transitory processor-readable medium for decoding a first codeword, comprising processor-readable instructions configured to cause one or more processors to:

obtain a first message comprising reliability information corresponding to each bit in the first codeword, wherein the first codeword comprises a first constituent codeword of a turbo product code (TPC) codeword;

determine a plurality of least reliable bits in the first codeword based on the reliability information, wherein a number of the plurality of least reliable bits is equal to a first parameter “L” of a Chase decoder, wherein the first parameter “L” represents “L” possible error locations in the first codeword;

generate, based on the Chase decoder, a plurality of flipped messages by flipping one or more of the plurality of least reliable bits in the first codeword, wherein a number of flipped bits in each of the plurality of flipped messages is limited to a second parameter “S” of the Chase decoder, wherein the second parameter “S” is smaller than the first parameter “L” and represents a maximum number of allowable bit-flips out of the “L” possible error locations; and

decode one or more of the plurality of flipped messages using at least the Chase decoder to generate one or more candidate codewords.

16. The processor-readable medium of claim 15 , wherein the processor-readable instructions are further configured to cause one or more processors to:

select a decoded message from the one or more candidate codewords based on a Euclidian distance of the one or more candidate codewords from the first codeword.

17. The processor-readable medium of claim 15 , wherein the second parameter is based on a latency simulation of the Chase decoder.

18. The processor-readable medium of claim 15 , wherein the processor-readable instructions are further configured to cause one or more processors to decode each of the plurality of flipped messages using the Chase decoder.

19. The processor-readable medium of claim 15 , wherein the first codeword is a Bose-Chaudhuri-Hocquenghem (BCH) codeword.

20. The processor-readable medium of claim 19 , wherein the TPC codeword comprises a plurality of constituent codewords, wherein the processor-readable instructions are further configured to cause one or more processors to:

decode the first constituent codeword of the TPC codeword in a set of decoding iterations by using the first parameter “L” and the second parameter “S;” and

decode a second constituent codeword of the TPC codeword in a subsequent set of decoding iterations by at least increasing the first parameter “L” to a third parameter “L” and increasing the second parameter “S” to a fourth parameter “S”.