IP Library › Granted Patent US 10,291,324
Granted Patent B2
US 10,291,324 · App. 15/438,659 · Granted May 14, 2019

Method of monitoring an optoelectronic transceiver with multiple flag values for a respective operating condition

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Quick Facts
Patent No.
US 10,291,324
App. No.
15/438,659
Granted
May 14, 2019
Kind
B2
Abstract

An optoelectronic transceiver includes an optoelectronic transmitter, an optoelectronic receiver, memory, and an interface. The memory is configured to store digital values representative of operating conditions of the optoelectronic transceiver. The interface is configured to receive from a host a request for data associated with a particular memory address, and respond to the host with a specific digital value of the digital values. The specific digital value is associated with the particular memory address received from the host. The optoelectronic transceiver may further include comparison logic configured to compare the digital values with limit values to generate flag values, wherein the flag values are stored as digital values in the memory.

Claims (91)

1. A circuit for monitoring operation of an optoelectronic transceiver, said circuit comprising:

a housing at least partially enclosing:

a laser transmitter and a photodiode receiver:

analog to digital conversion circuitry configured to convert a first analog signal corresponding to a first operating condition of said optoelectronic transceiver into a first digital value, and convert a second analog signal corresponding to a second operating condition of said optoelectronic transceiver into a second digital value;

memory configured to store the first and second digital values;

an interface configured to enable a host external to the optoelectronic transceiver to access the first and second digital values; and

one or more internal logic circuits coupled to the memory and configured to read from or write to the memory at least one of the first and second digital values;

wherein the circuit is configured to receive a disable command signal from the host to disable the laser transmitter.

2. The circuit of claim 1 , wherein the first digital value is selected from a group consisting of: a supply voltage measurement, a laser temperature measurement, a laser wavelength measurement, and a thermoelectric cooler current measurement.

3. The circuit of claim 1 , wherein the first digital value includes a supply voltage measurement.

4. The circuit of claim 1 , wherein the first digital value includes a laser temperature measurement.

5. The circuit of claim 1 , wherein the first digital value includes a laser wavelength measurement.

6. The circuit of claim 1 , wherein the first digital value includes a thermoelectric cooler current measurement.

7. The circuit of claim 1 , further comprising a processor configured to store the first digital value in a first memory location and to store the second digital value in a second memory location.

8. The circuit of claim 7 , wherein the processor is further configured to access the first digital value in the first memory location and to access the second digital value in the second memory location.

9. A circuit for monitoring operation of an optoelectronic transceiver, said circuit comprising:

a housing at least partially enclosing:

a laser transmitter and a photodiode receiver:

analog to digital conversion circuitry configured to convert a first analog signal corresponding to a first operating condition of said optoelectronic transceiver into a first digital value, and convert a second analog signal corresponding to a second operating condition of said optoelectronic transceiver into a second digital value;

memory configured to store the first and second digital values;

an interface configured to enable a host external to the optoelectronic transceiver to access the first and second digital values; and

a processor configured to access the first digital value in response to receiving a first address from the host and to access the second digital value in response to receiving a second address from the host.

10. The circuit of claim 9 , wherein the processor is further configured to provide the digital values accessed by the processor to the host via the interface.

11. The circuit of claim 1 , wherein the circuit further comprises control circuitry configured to generate control signals to control operation of the optoelectronic transceiver in accordance with one or more of the first digital value and the second digital value.

12. The circuit of claim 1 , wherein the circuit further comprises operation disable circuitry configured to disable operation of at least part of the optoelectronic transceiver in response to a signal, wherein the signal is based on one or more of the first digital value and the second digital value.

13. A circuit for monitoring operation of an optoelectronic transceiver, said circuit comprising:

a housing at least partially enclosing:

a laser transmitter and a photodiode receiver:

analog to digital conversion circuitry configured to convert a first analog signal corresponding to a first operating condition of said optoelectronic transceiver into a first digital value, and convert a second analog signal corresponding to a second operating condition of said optoelectronic transceiver into a second digital value;

memory configured to store the first and second digital values;

an interface configured to enable a host external to the optoelectronic transceiver to access the first and second digital values; and

rate selection circuitry configured to set the photodiode receiver to a bandwidth in response to a signal, wherein the signal is based on one or more of the first digital value and the second digital value.

14. A circuit for monitoring operation of an optoelectronic transceiver, said circuit comprising:

a housing at least partially enclosing:

a laser transmitter and a photodiode receiver:

analog to digital conversion circuitry configured to convert a first analog signal corresponding to a first operating condition of said optoelectronic transceiver into a first digital value, and convert a second analog signal corresponding to a second operating condition of said optoelectronic transceiver into a second digital value;

memory configured to store the first and second digital values;

comparison logic configured to compare the first digital value with a first limit value to generate a first flag value and to compare the second digital value with a second limit value to generate a second flag value, wherein the first and second flag values are stored in memory;

an interface configured to enable the host to access the first and second digital values and the first and second flag values; and

one or more internal logic circuits coupled to the memory and configured to read from or write to the memory at least one of the first digital value, the second digital value, the first flag value and the second flag value;

wherein the circuit is configured to receive a disable command signal from the host to disable the laser transmitter.

15. The circuit of claim 14 , further comprising a processor configured to store the first digital value in a first memory location, to store the second digital value in a second memory location, to store the first flag value in a first flag memory address, and to store the second flag value in a second flag memory address.

16. The circuit of claim 15 , wherein the processor is further configured to access the first digital value in the first memory location, to access the second digital value in the second memory location, to access the first flag value in the first flag memory address, and to access the second flag value in the second flag memory address.

17. A circuit for monitoring operation of an optoelectronic transceiver, said circuit comprising:

a housing at least partially enclosing:

a laser transmitter and a photodiode receiver:

analog to digital conversion circuitry configured to convert a first analog signal corresponding to a first operating condition of said optoelectronic transceiver into a first digital value, and convert a second analog signal corresponding to a second operating condition of said optoelectronic transceiver into a second digital value;

memory configured to store the first and second digital values;

comparison logic configured to compare the first digital value with a first limit value to generate a first flag value and to compare the second digital value with a second limit value to generate a second flag value, wherein the first and second flag values are stored in memory;

an interface configured to enable the host to access the first and second digital values and the first and second flag values; and

a processor configured to access the first digital value in response to receiving a first address from the host, to access the second digital value in response to receiving a second address from the host, to access the first flag value in response to receiving a first flag memory address, and to access the second flag value in response to receiving a second flag memory address.

18. The circuit of claim 17 , wherein the processor is further configured to provide the digital and flag values accessed by the processor to the host via the interface.

19. A circuit for monitoring operation of an optoelectronic transceiver, said circuit comprising:

a housing at least partially enclosing:

a laser transmitter and a photodiode receiver:

analog to digital conversion circuitry configured to convert a first analog signal corresponding to a first operating condition of said optoelectronic transceiver into a first digital value, and convert a second analog signal corresponding to a second operating condition of said optoelectronic transceiver into a second digital value;

memory configured to store the first and second digital values;

comparison logic configured to compare the first digital value with a first limit value to generate a first flag value and to compare the second digital value with a second limit value to generate a second flag value, wherein the first and second flag values are stored in memory;

an interface configured to enable the host to access the first and second digital values and the first and second flag values; and

control circuitry configured to generate control signals to control operation of the optoelectronic transceiver in accordance with one or more of the first flag value and the second flag value.

20. A circuit for monitoring operation of an optoelectronic transceiver, said circuit comprising:

a housing at least partially enclosing:

a laser transmitter and a photodiode receiver:

analog to digital conversion circuitry configured to convert a first analog signal corresponding to a first operating condition of said optoelectronic transceiver into a first digital value, and convert a second analog signal corresponding to a second operating condition of said optoelectronic transceiver into a second digital value;

memory configured to store the first and second digital values;

comparison logic configured to compare the first digital value with a first limit value to generate a first flag value and to compare the second digital value with a second limit value to generate a second flag value, wherein the first and second flag values are stored in memory;

an interface configured to enable the host to access the first and second digital values and the first and second flag values; and

operation disable circuitry configured to disable operation of at least part of the optoelectronic transceiver in response to a signal, wherein the signal is based on one or more of the first flag value and the second flag value.

21. The circuit of claim 9 , wherein the first digital value is selected from a group consisting of: a supply voltage measurement, a laser temperature measurement, a laser wavelength measurement, and a thermoelectric cooler current measurement.

22. The circuit of claim 9 , wherein the first digital value includes a supply voltage measurement.

23. The circuit of claim 9 , wherein the first digital value includes a laser temperature measurement.

24. The circuit of claim 9 , wherein the first digital value includes a laser wavelength measurement.

25. The circuit of claim 9 , wherein the first digital value includes a thermoelectric cooler current measurement.

26. The circuit of claim 9 , further comprising a processor configured to store the first digital value in a first memory location and to store the second digital value in a second memory location.

27. The circuit of claim 26 , wherein the processor is further configured to access the first digital value in the first memory location and to access the second digital value in the second memory location.

28. The circuit of claim 9 , wherein the circuit further comprises control circuitry configured to generate control signals to control operation of the optoelectronic transceiver in accordance with one or more of the first digital value and the second digital value.

29. The circuit of claim 9 , wherein the circuit further comprises operation disable circuitry configured to disable operation of at least part of the optoelectronic transceiver in response to a signal, wherein the signal is based on one or more of the first digital value and the second digital value.

30. The circuit of claim 13 , wherein the first digital value is selected from a group consisting of: a supply voltage measurement, a laser temperature measurement, a laser wavelength measurement, and a thermoelectric cooler current measurement.

31. The circuit of claim 13 , wherein the first digital value includes a supply voltage measurement.

32. The circuit of claim 13 , wherein the first digital value includes a laser temperature measurement.

33. The circuit of claim 13 , wherein the first digital value includes a laser wavelength measurement.

34. The circuit of claim 13 , wherein the first digital value includes a thermoelectric cooler current measurement.

35. The circuit of claim 13 , further comprising a processor configured to store the first digital value in a first memory location and to store the second digital value in a second memory location.

36. The circuit of claim 35 , wherein the processor is further configured to access the first digital value in the first memory location and to access the second digital value in the second memory location.

37. The circuit of claim 13 , wherein the circuit further comprises control circuitry configured to generate control signals to control operation of the optoelectronic transceiver in accordance with one or more of the first digital value and the second digital value.

38. The circuit of claim 13 , wherein the circuit further comprises operation disable circuitry configured to disable operation of at least part of the optoelectronic transceiver in response to a signal, wherein the signal is based on one or more of the first digital value and the second digital value.

39. The circuit of claim 17 , further comprising a processor configured to store the first digital value in a first memory location, to store the second digital value in a second memory location, to store the first flag value in a first flag memory address, and to store the second flag value in a second flag memory address.

40. The circuit of claim 19 , further comprising a processor configured to store the first digital value in a first memory location, to store the second digital value in a second memory location, to store the first flag value in a first flag memory address, and to store the second flag value in a second flag memory address.

41. The circuit of claim 40 , wherein the processor is further configured to access the first digital value in the first memory location, to access the second digital value in the second memory location, to access the first flag value in the first flag memory address, and to access the second flag value in the second flag memory address.

42. The circuit of claim 20 , further comprising a processor configured to store the first digital value in a first memory location, to store the second digital value in a second memory location, to store the first flag value in a first flag memory address, and to store the second flag value in a second flag memory address.

43. The circuit of claim 42 , wherein the processor is further configured to access the first digital value in the first memory location, to access the second digital value in the second memory location, to access the first flag value in the first flag memory address, and to access the second flag value in the second flag memory address.

Assignments (3)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: FINISAR CORPORATION
To: II-VI DELAWARE, INC.
Reel/Frame 052286/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →