Semiconductor nonvolatile memory element
View Patent ↗A semiconductor nonvolatile memory element is used to form a constant current source in a semiconductor integrated circuit device. The semiconductor nonvolatile memory element includes a control gate electrode, a floating gate electrode, source/drain terminals, a thin first gate insulating film, and a second gate insulating film that is thick enough not to be broken down even when a voltage higher than an operating voltage of the semiconductor integrated circuit device is applied thereto, the first and second gate insulating films being formed below the control gate electrode. Thus, provided is a normally on type semiconductor nonvolatile memory element in which a threshold voltage can be regulated through injection of a large amount of charge with respect to the operating voltage from a drain terminal into the floating gate electrode via the second gate insulating film, and injected carriers do not leak in an operating voltage range.
1. A semiconductor nonvolatile memory element, comprising:
a semiconductor substrate;
a well region of a first conductivity type formed in the semiconductor substrate;
a heavily doped source region and a first heavily doped drain region which are formed in the well region so as to be apart from each other, and each of which contains high-concentration impurities of a second conductivity type;
a first gate insulating film formed on the semiconductor substrate between the heavily doped source region and the first heavily doped drain region so as to be adjacent to the heavily doped source region;
a second gate insulating film formed on the semiconductor substrate between the heavily doped source region and the first heavily doped drain region so as to be adjacent to the first heavily doped drain region;
a second heavily doped drain region of the second conductivity type formed apart from the heavily doped source region, the second heavily doped drain region including a region under the second gate insulating film and being formed in a region that overlaps the first heavily doped drain region;
a first lightly doped drain region of the second conductivity type formed apart from the heavily doped source region, the first lightly doped drain region including the a region under the first gate insulating film and a region under the second gate insulating film and being formed in a region that overlaps the first heavily doped drain region and the second heavily doped drain region;
a channel impurity region of the second conductivity type formed under the first gate insulating film between the heavily doped source region and the first lightly doped drain region;
a floating gate electrode that is made of polycrystalline silicon containing high-concentration impurities, and is formed on the first gate insulating film and the second gate insulating film;
a control gate electrode formed in the well region formed at a location apart from the channel impurity region, the control gate electrode comprising a diffusion region containing high-concentration impurities of the second conductivity type; and
a third gate insulating film formed between the floating gate electrode that extends to above the diffusion region serving as the control gate electrode and the diffusion region serving as the control gate electrode,
wherein the second gate insulating film has a thickness that is larger than a thickness of the first gate insulating film, and
wherein the well region includes the heavily doped source region, the first heavily doped drain region, the second heavily doped drain region, the first lightly doped drain region, and the channel impurity region, and is formed to a depth that is larger than depths of the heavily doped source region, the first heavily doped drain region, the second heavily doped drain region, the first lightly doped drain region, and the channel impurity region.
2. A semiconductor nonvolatile memory element according to claim 1 ,
wherein the impurities in the first heavily doped drain region comprise one of As and P at a concentration of 1×10 20 /cm 3 or more,
wherein impurities in the second heavily doped drain region comprise one of As and P at a concentration of 5×10 18 /cm 3 or more,
wherein impurities in the first lightly doped drain region comprise one of As and P at a concentration of 1×10 17 /cm 3 or more and 1×10 18 /cm 3 or less, and
wherein impurities in the well region comprise boron at a concentration of from 7×10 15 /cm 3 to 7×10 16 /cm 3 .
3. A semiconductor nonvolatile memory element according to claim 1 , wherein the first gate insulating film has a thickness of from 100 Å to 200 Å.
4. A semiconductor nonvolatile memory element according to claim 1 , wherein the first gate insulating film comprises SiON and the second gate insulating film comprises SiO 2 .
5. A semiconductor nonvolatile memory element according to claim 1 , wherein the first gate insulating film comprises SiN and the second gate insulating film comprises SiO 2 .