Dynamic calibration for transceivers
The present disclosure relates to a method and system for calibrating transceivers by providing a stored index that was calculated of a race condition count. The race condition is based at least in part to a rat race between a clock signal and an input signal that has been sampled by a random or jitter signal. The stored index corresponds to a relative timing error between the clock signal and the sampled input signal. The stored index is used to scramble subsequent input signals that are thermo-coded signals, thereby eliminating timing errors.
1. A method for calibration of a transceiver comprising:
providing a jitter signal to the transceiver;
sampling an input signal in accordance with the jitter signal to provide a sampled input signal;
receiving, at an electronic element in the transceiver, the sampled input signal and a clock signal;
determining that a race condition exists between the sampled input signal and the clock signal;
revising a count value in accordance with the determination of the race condition;
calculating, from the count value, a relative timing error between the sampled input signal and the clock signal; and
scrambling an output signal from the electronic element to provide scrambled output signal, the scrambling in accordance with an index corresponding to the relative timing error, the index stored for use with subsequent input signals to the transceiver.
2. The method of claim 1 , wherein the providing for the jitter signal is by a signal generator that is configured to add randomness to the clock signal using a seed number input from a register.
3. The method of claim 1 , wherein the providing for the jitter signal is by a signal generator that is configured to add noise to the clock signal using a linear feedback shift register (LFSR).
4. The method of claim 1 , wherein the determination of the race condition is performed by a comparison of receipt times of edges of the sampled input signal and the clock signal, and the comparison occurring when the sampled input signal and the clock signal are active in a predetermined time interval.
5. The method of claim 4 , wherein the determination of the race condition further comprises using a sub-pico second difference in the comparison of the receipt times of the edges of the sampled input signal and the clock signal.
6. The method of claim 1 , wherein the electronic element is one among flip-flops or registers.
7. The method of claim 1 , wherein the sampled input signal and the output signal are thermometer-coded signals.
8. The method of claim 1 , wherein the index maps the sampled input signal and the output signal.
9. The method of claim 1 , wherein the index comprises code for controlling signal selection to output the scrambled output signal.
10. The method of claim 1 , further comprising: pre-calibrating of the clock signal and the input signal to synchronize the clock signal and the input signal.
11. A transceiver circuit, comprising:
a signal generator for providing a jitter signal;
a sampler circuit for sampling an input signal in accordance with the jitter signal to provide a sampled input signal;
an electronic element in the transceiver circuit, receiving the sampled input signal and a clock signal;
a sensor circuit for determining that a race condition exists between the sampled input signal and the clock signal;
the sensor circuit for revising a count value in accordance with the determination of the race condition;
the sensor circuit for calculating, from the count value, a relative timing error between the respective sampled input signals and the clock signal; and
a scrambler circuit for scrambling an output signal from the electronic element to provide a scrambled output signal, the scrambling in accordance with an index corresponding to the relative timing error, the index stored for use with subsequent input signals to the transceiver.
12. The transceiver circuit of claim 11 , wherein the signal generator is configured to add randomness to the clock signal using a seed number, from a register, for the providing of the jitter signal.
13. The transceiver circuit of claim 11 , wherein the signal generator is configured to add noise to the clock signal using a linear feedback shift register (LFSR), for the providing of the jitter signal.
14. The transceiver circuit of claim 11 , wherein the sensor circuit is configured for the determining of the race condition by comparing receipt times of edges of the sampled input signal and the clock signal, the comparing performed when the sampled input signal and the clock signal are active in a predetermined time interval.
15. The transceiver circuit of claim 14 , wherein the sensor circuit is configured for the comparing of the receipt times using a sub-pico second difference in the receipt times of the edges of the sampled input signal and the clock signal.
16. The transceiver circuit of claim 14 , wherein the electronic element is one among flip-flops or registers.
17. The transceiver circuit of claim 14 , wherein the sampled input signal and output signal are thermometer-coded signals.
18. The transceiver circuit of claim 14 , wherein the index maps the sampled input signals and the output signals.
19. The transceiver circuit of claim 14 , wherein the index comprises code for controlling signal selection to output the scrambled output signal.
20. The transceiver circuit of claim 14 , further comprising a pre-calibration circuit for pre-calibration of the clock signal and the input signal to synchronize the clock signal and the input signal.