Memory system storing block protection information

1. A memory system comprising:

a controller that recognizes, as a command, a signal received immediately after a chip select signal is received from a host device; and

a memory that includes a plurality of blocks,

wherein the controller includes a storage area in which block protection information for the plurality of blocks is maintained, and

wherein, when the command is a first command, the controller outputs to the host device, information indicating whether at least one of a write operation and an erase operation with respect to at least one particular block of the plurality of blocks is prohibited, the controller determining the information based on the block protection information maintained in the storage area of the controller, and

when the command is a second command, the controller, in response to the second command, determines whether a block specified by the host device with the second command corresponds to a protectable user block, updates the block protection information maintained in the storage area of the controller to prohibit at least one of a write operation or an erase operation with respect to the block specified by the host device with the second command upon determining that the block specified by the host device with the second command corresponds to a protectable user block, and does not update the block protection information maintained in the storage area of the controller upon determining that the block specified by the host device with the second command does not correspond to a protectable user block,

wherein the memory does not maintain a copy of the block protection information.

2. The memory system according to claim 1 , wherein

the second command includes an address of the particular block.

3. The memory system according to claim 2 , wherein

in response to the first command, the controller additionally outputs the information for a plurality of blocks having addresses that are contiguous to the address of the particular block.

4. The memory system according to claim 1 , wherein

the information indicates whether the write operation is prohibited, and whether the erasing operation is prohibited.

5. The memory system according to claim 1 , wherein the signal is received in synchronism with a next clock signal following the chip select signal.

6. The memory system according to claim 5 , wherein the host interface circuit is an SPI interface circuit.

7. A memory system comprising:

a nonvolatile semiconductor memory including a plurality of blocks;

a host interface circuit having no more than eight pins connectable to a host; and

a memory controller including a storage area in which block protection data indicative of whether or not a particular block of the plurality of blocks is protected from writing or erasing is maintained, the memory controller configured to output the block protection data to the host through the host interface circuit in response to a first command received from the host through the host interface circuit, wherein

in response to a second command received from the host through the host interface circuit, the memory controller determines whether a block specified by the host device with the second command corresponds to a protectable block, updates the block protection data maintained in the storage area of the memory controller to prohibit at least one of a write operation or an erase operation with respect to the block specified by the host device with the second command upon determining that the block specified by the host device with the second command corresponds to a protectable block, and does not update the block protection data maintained in the storage area of the memory controller upon determining that the block specified by the host device with the second command does not correspond to a protectable block,

wherein the nonvolatile semiconductor memory does not maintain a copy of the block protection information.

8. The memory system according to claim 7 , wherein the first command includes an address of the particular block.

9. The memory system according to claim 7 , wherein the memory controller is configured to store block protection data for another block of the plurality of blocks in the storage area in response to the second command received from the host through the host interface circuit, the second command including an address of said another block.

10. The memory system according to claim 7 , wherein the block protection data includes first data indicating whether or not the particular block is protected from writing and second data indicating whether or not the particular block is protected from erasing.

11. The memory system according to claim 7 , wherein the pins include a first pin for a chip select signal, a second pin for a ground connection, a third pin for a power supply connection, and a fourth pin for a serial clock signal.

12. The memory system according to claim 11 , wherein the first command is received through a fifth pin of the host interface circuit in synchronism with a next serial clock signal received following the chip select signal asserted on the first pin.

13. The memory system according to claim 12 , wherein the host interface circuit is an SPI interface circuit.

14. A memory system comprising:

a controller that recognizes, as a command, a signal received immediately after a chip select signal is received from a host device; and

a memory that includes a plurality of blocks,

wherein the controller includes a block protection register in which block protection information for the plurality of blocks is stored and a status register in which information indicating a status of the command received from the host device is stored, and

wherein, when the command is a first command, the controller outputs to the host device, information indicating whether a write or erase operation with respect to at least one particular block of the plurality of blocks has failed, when the controller determines from the block protection information stored in the block protection register of the controller that the write or erase operation is prohibited with respect to the at least one particular block, and

wherein, when the command is a second command, the controller, in response to the second command, determines whether a block specified by the host device with the second command corresponds to a protectable user block, and

(i) upon determining that the block specified by the host device with the second command corresponds to a protectable user block, updates the block protection information stored in the block protection register of the controller to prohibit the write or erase operation with respect to the block specified by the host device with the second command, and updates the status register to indicate that the second command has passed, and

(ii) upon determining that the block specified by the host device with the second command does not correspond to a protectable user block, does not update the block protection information stored in the block protection register of the controller, and updates the status register to indicate that the second command has failed.