IP Library Granted Patent US 11,264,548
Granted Patent B2
US 11,264,548 · App. 15/441,074 · Granted Mar 1, 2022

Low profile interconnect for light emitter

Inventor: Kevin Curtis (Boulder, CO)
Assignee: Magic Leap, Inc.
H01L33/62G02B6/001G02B6/005G02B6/0028G02B6/0076G02B27/017G02B27/0172G02B2027/0118G02B2027/0134G02B2027/0178H01L33/385H01L33/52H01L2224/24225H01L2224/73265H01L2933/0066
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Quick Facts
Patent No.
US 11,264,548
App. No.
15/441,074
Granted
Mar 1, 2022
Kind
B2
Abstract

In some embodiments, an interconnect electrical connects a light emitter to wiring on a substrate. The interconnect may be deposited by 3D printing and lays flat on the light emitter and substrate. In some embodiments, the interconnect has a generally rectangular or oval cross-sectional profile and extends above the light emitter to a height of about 50 μm or less, or about 35 μm or less. This small height allows close spacing between an overlying optical structure and the light emitter, thereby providing high efficiency in the injection of light from the light emitter into the optical structure, such as a light pipe.

Claims (18)

1. A display system, comprising:

a substrate comprising a plurality of substrate bond pads;

an array of light emitters attached to the substrate, each of the light emitters comprising a light emitter bond pad and having horizontal and vertical surfaces;

an electrical interconnect over each of the light emitters, the electrical interconnect contacting an associated light emitter bond pad at one end of the electrical interconnect and contacting an associated substrate bond pad at an other end of the electrical interconnect,

wherein a cross-sectional shape of the electrical interconnect, as viewed in a plane transverse to an elongate axis of the electrical interconnect, has a width larger than a height of the cross-sectional shape by a factor of 50 or more, and wherein the electrical interconnect conformally follows and mimics a contour defined by the vertical and horizontal surfaces of the associated light emitter;

a plurality of light pipes, wherein each of the light pipes is over an exposed surface of an electrical interconnect of a corresponding light emitter of the plurality of light emitters, wherein each of the light pipes is separated by an air gap from the exposed surface of the electrical interconnect;

a spatial light modulator configured to receive light from the light pipes and to modulate the light to define images; and

a plurality of waveguides forming a waveguide stack, each waveguide comprising a light incoupling optical element configured to receive light from a corresponding one of the light pipes after the light is modulated by the spatial light modulator.

2. The display system of claim 1 , wherein a maximum height of the electrical interconnect above each light emitter is 50 μm or less.

3. The display system of claim 1 , wherein the light emitter defines a step over the substrate, wherein the electrical interconnect follows contours of the step.

4. The display system of claim 1 , wherein the cross-sectional shape is rectangular.

5. The display system of claim 1 , wherein the electrical interconnect comprises a metal.

6. The display system of claim 1 , wherein the light emitter is a LED chip.

7. The display system of claim 1 , wherein the substrate is a printed circuit board.

8. The display system of claim 1 , further comprising a dielectric layer between the light emitter and the electrical interconnect.

9. The display system of claim 1 , further comprising a reflector over an exposed surface of the light emitter.

10. The display system of claim 9 , further comprising a plurality of the reflectors, each reflector configured to direct light to the spatial light modulator.

11. The display system of claim 1 , wherein each of the light pipes comprises a light output end for outputting the received light to the spatial light modulator, wherein light output ends of some of the light pipes have a different area size than light output ends of others of the light pipes.

Assignments (3)
ASSIGNMENT OF SECURITY INTEREST IN PATENTS Recorded Nov 7, 2019
From: JPMORGAN CHASE BANK, N.A.
To: CITIBANK, N.A.
Reel/Frame 050967/0138 →
PATENT SECURITY AGREEMENT Recorded Aug 22, 2019
From: MAGIC LEAP, INC.; MOLECULAR IMPRINTS, INC.; MENTOR ACQUISITION ONE, LLC
To: JP MORGAN CHASE BANK, N.A.
Reel/Frame 050138/0287 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 19, 2017
From: CURTIS, KEVIN
To: MAGIC LEAP, INC.
Reel/Frame 043042/0503 →
Continuity (2)
Provisional Application 62299163 · Feb 24, 2016
Related Publication 20170244013A1 · Aug 24, 2017
Cited By (1)
US 12,369,444