Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
1. An integrated circuit block comprising:
a first node;
a second node;
a series arrangement of one or more capacitive elements; and
a series arrangement of three or more switches;
wherein:
the one or more capacitive elements are in series with the three or more switches regardless of states of switches of the three or more switches;
a combination of the one or more capacitive elements and the three or more switches is coupled between the first node and the second node;
the three or more switches are configured to withstand a voltage greater than a voltage withstood by one switch;
the three or more switches are configured to receive a control signal to enable or disable the switches and thereby adjusting the capacitance between the two nodes, and
compensation capacitive elements are coupled across at least one of the three or more switches.
2. The integrated circuit block of claim 1 , wherein the three or more switches comprise FET switches.
3. The integrated circuit block of claim 2 , wherein the compensation capacitive elements comprise metal-based capacitors.
4. The integrated circuit block of claim 3 , wherein the metal-based capacitors comprise Metal-Metal (MM) capacitors.
5. The integrated circuit block of claim 1 , wherein the compensation capacitive elements provide capacitance values that are symmetrical with reference to a node within the integrated circuit block.
6. The integrated circuit block of claim 1 , wherein compensation capacitive elements are coupled across at least one of the three or more switches, the at least one of the three or more switches being closer to either of the first node or the second node than the other of the first node or the second node.
7. A Digitally Tuned Capacitor (DTC) comprising a plurality of the integrated circuit blocks of claim 5 or 6 , wherein the plurality of the integrated circuit blocks are configured in parallel.
8. An integrated circuit block comprising:
a first node;
a second node;
a series arrangement of one or more capacitive; and
wherein:
the one or more capacitive elements are in series with the two or more switches regardless of states of switches of the two or more switches;
a combination of the one or more capacitive elements and the two or more switches is coupled between the first node and the second node;
the two or more switches are configured to withstand a voltage greater than a voltage withstood by one switch;
each of the two or more switches has a control node connected to a control signal via a resistive element;
the control signal is configured to enable or disable the two or more switches and thereby adjusting the capacitance between the first node and the second node, and
compensation capacitive elements are coupled across at least one of the two or more switches.
9. The integrated circuit block of claim 8 , wherein the two or more switches comprise FET switches.
10. The integrated circuit block of claim 9 , wherein the compensation capacitive elements comprise metal-based capacitors.
11. The integrated circuit block of claim 10 , wherein the metal-based capacitors comprise Metal-Metal (MM) capacitors.
12. The integrated circuit block of claim 8 , wherein the compensation capacitive elements provide capacitance values that are symmetrical with reference to a node within the integrated circuit block.
13. The integrated circuit block of claim 8 , wherein compensation capacitive elements are coupled across at least one of the two or more switches, the at least one of the two or more switches being closer to either of the first node or the second node than the other of the first node or the second node.
14. A Digitally Tuned Capacitor (DTC) comprising a plurality of the integrated circuit blocks of claim 12 or 13 , wherein the plurality of the integrated circuit blocks are configured in parallel.