Semiconductor memory device

1. A semiconductor memory device comprising:

a first circuit configured to process data received from and transmitted to an external controller;

a second circuit configured to execute calibration on the first circuit; and

a control circuit configured to control the second circuit to execute the calibration on the first circuit in response to a calibration command received from the external controller, wherein

in response to a first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit, and

in response to a second calibration command that is received after the first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit if a first condition is met and to not execute the calibration on the first circuit if the first condition is not met, and

a command sequence for the first calibration command received from the controller and a command sequence for the second calibration command received from the controller are different.

2. The device according to claim 1 , wherein the first condition is met when a change in a temperature of the first circuit exceeds a threshold.

3. The device according to claim 2 , wherein the second circuit includes a temperature measurement circuit that measures a first temperature of the first circuit at a time of the first calibration command and a second temperature of the first circuit at a time of the second calibration command, and the change is equal to a difference in the first and second measured temperatures.

4. The device according to claim 2 , wherein the second circuit includes a temperature measurement circuit that measures a first temperature of the first circuit during a first core operation prior to the first calibration command and a second temperature of the first circuit during a second core operation after the first calibration command and prior to the second calibration command, and the change is equal to a difference in the first and second measured temperatures.

5. The device according to claim 1 , wherein the first condition is met when a change in a voltage applied to the first circuit exceeds a threshold.

6. The device according to claim 5 , wherein the second circuit includes a voltage measurement circuit that measures a first voltage applied to the first circuit at a time of the first calibration command and a second voltage applied to the first circuit at a time of the second calibration command, and the change is equal to a difference in the first and second measured voltages.

7. The device according to claim 5 , wherein the second circuit includes a voltage measurement circuit that measures a first voltage applied to the first circuit during a first core operation prior to the first calibration command and a second voltage applied to the first circuit during a second core operation after the first calibration command and prior to the second calibration command, and the change is equal to a difference in the first and second measured voltages.

8. The device according to claim 1 , wherein the second circuit is configured to calibrate an impedance of the first circuit.

9. A semiconductor memory device comprising:

a first circuit configured to process data received from and transmitted to an external controller;

a second circuit configured to execute calibration on the first circuit; and

a control circuit configured to control the second circuit to execute the calibration on the first circuit in response to a calibration command received from the external controller, wherein

in response to a first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit, and

in response to a second calibration command that is received after the first calibration command, the control circuit controls the second circuit to execute the calibration on the first circuit if a first condition is met and to not execute the calibration on the first circuit if the first condition is not met, and

a command sequence for the first calibration command received from the controller and a command sequence for the second calibration command received from the controller are the same.

10. A method of managing calibrations executed on an input/output circuit of a semiconductor memory device that performs operations therein in response to commands received from a controller, said method comprising:

executing a first calibration on the input/output circuit in response to a first calibration command received from the controller;

in response to a second calibration command that is received after the first calibration command, determining if a first condition is met; and

executing a second calibration on the input/output circuit if the first condition is met but not executing the second calibration on the input/output circuit if the first condition is not met, wherein

a command sequence for the first calibration command received from the controller and a command sequence for the second calibration command received from the controller are different.

11. The method according to claim 10 , wherein the first condition is met when a change in a temperature of the input/output circuit exceeds a threshold.

12. The method according to claim 11 , further comprising:

measuring a first temperature of the input/output circuit at a time of the first calibration command and a second temperature of the input/output circuit at a time of the second calibration command, wherein the change is equal to a difference in the first and second measured temperatures.

13. The method according to claim 11 , further comprising:

measuring a first temperature of the first circuit during a first core operation that is executed prior to receipt of the first calibration command and a second temperature of the first circuit during a second core operation executed after receipt of the first calibration command and prior to receipt of the second calibration command, and the change is equal to a difference in the first and second measured temperatures.

14. The method according to claim 10 , wherein the first condition is met when a change in a voltage applied to the first circuit exceeds a threshold.

15. The method according to claim 14 , further comprising:

measuring a first voltage applied to the first circuit at a time of the first calibration command and a second voltage applied to the first circuit at a time of the second calibration command, wherein the change is equal to a difference in the first and second measured voltages.

16. The method according to claim 14 , further comprising:

measuring a first voltage applied to the first circuit during a first core operation executed prior to receipt of the first calibration command and a second voltage applied to the first circuit during a second core operation executed after receipt of the first calibration command and prior to receipt of the second calibration command, wherein the change is equal to a difference in the first and second measured voltages.

17. The method according to claim 10 , wherein the calibrations are executed on the input/output circuit to calibrate an impedance of the input/output circuit.

18. A method of managing calibrations executed on an input/output circuit of a semiconductor memory device that performs operations therein in response to commands received from a controller, said method comprising:

executing a first calibration on the input/output circuit in response to a first calibration command received from the controller;

in response to a second calibration command that is received after the first calibration command, determining if a first condition is met; and

executing a second calibration on the input/output circuit if the first condition is met but not executing the second calibration on the input/output circuit if the first condition is not met, wherein

a command sequence for the first calibration command received from the controller and a command sequence for the second calibration command received from the controller are the same.