System and method for data restore flexibility on dual channel NVDIMMs
View Patent ↗A DIMM includes first and second DRAM devices, each configured to perform memory transactions for memory locations associated with the DRAM device via a respective first and second memory channel. The DIMM also includes a non-volatile memory device and a DIMM controller. The DIMM controller stores data from the first and second memory locations to the non-volatile memory device in response to a save data operation, receives an indication that communication via the first memory channel has failed, stores the first data from the non-volatile memory device to the second DRAM device in response to the indication and a restore data operation, provides an indication that the data is stored on the second DRAM device, receives an indication that the data has been read, stores the second data from the non-volatile memory device to the second DRAM device, and provides an indication that the second data is stored on the second DRAM device.
1. A Dual In-Line Memory Module (DIMM), comprising:
a first Dynamic Random Access Memory (DRAM) device configured to perform memory transactions for first memory locations associated with the first DRAM device via a first memory channel;
a second DRAM device configured to perform memory transactions for second memory locations associated with the second DRAM device via a second memory channel;
a non-volatile memory device; and
a DIMM controller configured to:
store first data from the first memory locations and second data from the second memory locations to the non-volatile memory device in response to a save data operation from a memory controller;
receive a first indication that communication via the first memory channel has failed;
store the first data from the non-volatile memory device to the second DRAM device in response to the first indication and in response to a restore data operation from the memory controller;
provide a second indication that the first data is stored on the second DRAM device;
receive a third indication that the first data has been read by the memory controller;
store the second data from the non-volatile memory device to the second DRAM device in response to the third indication; and
provide a fourth indication that the second data is stored on the second DRAM device.
2. The DIMM of claim 1 , wherein, in further response to the restore data operation, the DIMM controller is further configured to:
isolate the first DRAM device and the second DRAM device from the memory controller.
3. The DIMM of claim 2 , wherein after providing the second indication, the DIMM controller is further configured to:
couple the second DRAM device to the memory controller.
4. The DIMM of claim 3 , further comprising:
a first multiplexor coupled to the first DRAM device and configured to selectably couple the first DRAM device to the memory controller and to the DIMM controller; and
a second multiplexor coupled to the second DRAM device and configured to selectably couple the second DRAM device to the memory controller and to the DIMM controller.
5. The DIMM of claim 4 , wherein, in isolating the first DRAM device and the second DRAM device from the memory controller, the DIMM controller is further configured to:
select the first multiplexor to couple the first DRAM device to the DIMM controller; and
select the second multiplexor to couple the second DRAM device to the DIMM controller.
6. The DIMM of claim 5 , wherein, in coupling the second DRAM device to the memory controller, the DIMM controller is further configured to:
select the second multiplexor to couple the second DRAM device to the memory controller.
7. The DIMM of claim 1 , wherein the first DRAM device has a first storage capacity, the second DRAM device has a second storage capacity, and the non-volatile memory device has a third storage capacity, the third storage capacity being greater than a sum of the first storage capacity and the second storage capacity.
8. The DIMM of claim 7 , wherein the DIMM comprises a N-type non-volatile DIMM (NVDIMM-N).
9. The DIMM of claim 1 , wherein the DIMM comprises a fifth generation Double Data Rate (DDR5) DIMM.
10. A method, comprising:
providing, on a Dual In-Line Memory Module (DIMM), a first Dynamic Random Access Memory (DRAM) device configured to perform memory transactions for first memory locations associated with the first DRAM device via a first memory channel;
providing, on the DIMM, a second DRAM device configured to perform memory transactions for second memory locations associated with the second DRAM device via a second memory channel;
storing, on a non-volatile memory device of the DIMM, first data from the first memory locations and second data from the second memory locations to the non-volatile memory device in response to a save data operation from a memory controller;
receiving a first indication that communication via the first memory channel has failed;
storing the first data from the non-volatile memory device to the second DRAM device in response to the first indication and to a restore data operation from the memory controller;
providing a second indication that the first data is stored on the second DRAM device;
receiving a third indication that the first data has been read by the memory controller;
storing the second data from the non-volatile memory device to the second DRAM device in response to the third indication; and
providing a fourth indication that the second data is stored on the second DRAM device.
11. The method of claim 10 , further comprising:
isolating the first DRAM device and the second DRAM device from the memory controller in further response to the restore data operation.
12. The method of claim 11 , further comprising:
coupling the second DRAM device to the memory controller after providing the second indication.
13. The method of claim 12 , further comprising:
coupling a first multiplexor to the first DRAM device, the first multiplexor being configured to selectably couple the first DRAM device to the memory controller and to the DIMM controller; and
coupling a second multiplexor to the second DRAM device, the second multiplexor being configured to selectably couple the second DRAM device to the memory controller and to the DIMM controller.
14. The method of claim 13 , wherein, in isolating the first DRAM device and the second DRAM device from the memory controller, the method further comprises:
selecting the first multiplexor to couple the first DRAM device to the DIMM controller; and
selecting the second multiplexor to couple the second DRAM device to the DIMM controller.
15. The method of claim 14 , wherein, in coupling the second DRAM device to the memory controller, the method further comprises:
selecting the second multiplexor to couple the second DRAM device to the memory controller.
16. The method of claim 10 , wherein the first DRAM device has a first storage capacity, the second DRAM device has a second storage capacity, and the non-volatile memory device has a third storage capacity, the third storage capacity being greater than a sum of the first storage capacity and the second storage capacity.
17. The method of claim 16 , wherein the DIMM comprises a N-type non-volatile DIMM (NVDIMM-N).
18. The method of claim 10 , wherein the DIMM comprises a fifth generation Double Data Rate (DDR5) DIMM.
19. An information handling system, comprising:
a memory controller; and
a Dual In-Line Memory Module (DIMM), including a first Dynamic Random Access Memory (DRAM) device configured to perform memory transactions for first memory locations associated with the first DRAM device via a first memory channel, a second DRAM device configured to perform memory transactions for second memory locations associated with the second DRAM device via a second memory channel, a non-volatile memory device, and a DIMM controller configured to:
store first data from the first memory locations and second data from the second memory locations to the non-volatile memory device in response to a save data operation from the memory controller;
receive a first indication that communication via the first memory channel has failed;
store the first data from the non-volatile memory device to the second DRAM device in response to the first indication and to a restore data operation from the memory controller;
provide a second indication that the first data is stored on the second DRAM device;
receive a third indication that the first data has been read by the memory controller;
store the second data from the non-volatile memory device to the second DRAM device in response to the third indication; and
provide a fourth indication that the second data is stored on the second DRAM device.
20. The information handling system of claim 19 , wherein the DIMM further includes a first multiplexor coupled to the first DRAM device and configured to selectably couple the first DRAM device to the memory controller and to the DIMM controller, and a second multiplexor coupled to the second DRAM device and configured to selectably couple the second DRAM device to the memory controller and to the DIMM controller.