Memory system using message monitoring and first and second namespaces
According to one embodiment, a memory system includes a first memory including a message queue having first to n th addresses (n≥2, n is natural number), a first pointer showing one of the first to n th addresses, and a second pointer showing one of the first to n th addresses, a monitor unit which detects whether the first and second pointers show the first address, and a processing unit which changes an address shown by the first pointer from the first address to an i th address (n≥i≥2, i is natural number) when the first and second pointers show the first address. An address shown by the second pointer is incremented from the first address to a (j+1) th address (j≥1, j is natural number) when first to j th messages are queued in the first to j th addresses.
1. A memory system comprising:
a first memory including a message queue having first to n th addresses (n is a natural number greater than or equal to 2), a first pointer showing one of the first to n th addresses, and a second pointer showing one of the first to n th addresses;
a monitor unit which detects whether the first and second pointers show the first address; and
a processing unit which changes an address shown by the first pointer from the first address to an i th address (i is a natural number greater than or equal to 2 and less than or equal to n) when the first and second pointers show the first address,
wherein an address shown by the second pointer is incremented from the first address to a (j+1) th address (j is a natural number greater than or equal to 1) when first to j th messages are queued in the first to j th addresses,
the monitor unit outputs information when (j+1) is equal to i, and
the processing unit processes the first to j th messages on the basis of the information.
2. The system of claim 1 , wherein the processing unit changes the address shown by the first pointer from the first address to a (k+1) address when k messages (k is a natural number greater than or equal to 2) are to be processed in parallel.
3. The system of claim 1 , wherein the first to j th messages are transferred from a message source, and the message source increments the address shown by the second pointer.
4. The system of claim 3 , wherein the message source is a CPU or a hardware engine.
5. The system of claim 3 , wherein the processing unit and the message source are CPUs, respectively.
6. The system of claim 1 , wherein the processing unit changes the address shown by the first pointer from the i th address to an I th address (where I is a natural number greater than or equal to 2 and less than or equal to n) after receiving the information.
7. The system of claim 1 , wherein the first memory includes an error queue showing whether the first to j th messages queued in the first to j th addresses include an error.
8. The system of claim 1 , further comprising:
a second memory as a nonvolatile memory,
wherein the first to j th messages are responses of read commands to the second memory.
9. The system of claim 1 , further comprising:
a second memory as a nonvolatile memory,
wherein the monitor unit and the processing unit are provided in a controller which controls the second memory.
10. The system of claim 9 , wherein the first memory is provided in the controller.
11. A memory system which is connectable to a host, the system comprising:
a first memory storing user data and a table, the table being used for translating a first address into a second address when the host accesses the user data: and
a controller which translates the first address into the second address by referring to the table,
wherein the host manages a namespace which is storable in the table,
the namespace includes chunks each having a given capacity of A=C max /Y and each corresponding to a plurality of second addresses, where C max is a maximum capacity of the namespace and Y is a natural number greater than or equal to 2, and
the first address is translated into one of the plurality of second addresses through one of the chunks.
12. The system of claim 11 , wherein a number of the chunks in the namespace is determined on the basis of a capacity of the namespace provided by the host.
13. The system of claim 11 , wherein a total number of the chunks is N=(X+Y), where X is a maximum number of namespaces which is managed by the host, and X and Y satisfy the relationship of Y≥X.
14. The system of claim 13 , wherein Y is a maximum number of the chunks which is assignable in one namespace.
15. The system of claim 13 , wherein A×N is greater than a capacity of the first memory.
16. The system of claim 11 , wherein the first address is an address of a first data unit which is managed by the host, and the second address is an address of a read/write unit of the first memory.
17. The system of claim 11 , wherein the first memory is a nonvolatile memory as a storage memory.
18. The system of claim 11 , wherein the controller includes a second memory storing the table stored in the first memory as cache data.
19. The system of claim 11 , further comprising a second memory storing the table stored in the first memory as cache data.
20. The system of claim 11 , wherein the table shows association between the first address and the chunks and association between the chunks and the second address.