Display device and electronic apparatus
According to an aspect, a display device includes: a display unit that has a plurality of scanning signal lines to which a scanning signal is applied; a shift register that has a plurality of transfer circuits configured in a plurality of stages that perform a shift operation for temporarily storing a shift signal that has been input and sequentially transmitting the stored shift signal to a subsequent stage in synchronization with a clock signal having a discontinued period, and outputs the scanning signal to a scanning signal line corresponding to a transfer circuit that maintains the shift signal; and a signal line that transmits a holding potential signal for maintaining a potential of the shift signal to a transfer circuit that maintains the shift signal in the discontinued period of the clock signal.
1. A display device comprising:
a plurality of gate lines including a first gate line, a first second gate line, and a second second gate line; and
a shift register including transfer circuits including
a first transfer circuit, and
a plurality of second transfer circuits including a first second transfer circuit and a second second transfer circuit, the transfer circuits each comprising:
an output terminal;
a first switch having a first gate, a first source, and a first drain, one of the first source and the first drain being connected to a first signal line, and the other of the first source and the first drain being connected to the output terminal;
a second switch having a second gate, a second source, and a second drain,
wherein:
in the first second transfer circuit,
one of the second source and the second drain is connected to the first gate, and
the output terminal is connected to the first second gate line and the second gate of the first transfer circuit;
in the first transfer circuit,
one of the second source and the second drain is connected to the first gate,
the other of the second source and the second drain is connected to a second signal line different from the first gate line and the first second gate line; and
in the second second transfer circuit,
one of the second source and the second drain is connected to the first gate,
the other of the second source and the second drain is connected to the first gate line connected to the output terminal of the first transfer circuit, and
the output terminal is connected to the second second gate line.
2. The display device according to claim 1 , wherein
the one of the first source and the first drain is connected to the first signal line,
each of the transfer circuits further comprises a first capacitor having
a first C 1 -terminal connected to the first gate and
a second C 1 -terminal connected to the other of the first source and the first drain.
3. The display device according to claim 2 , wherein
each of the transfer circuits further comprises
a second capacitor and
a fourth switch having a fourth gate, a fourth source, and a fourth drain,
the second capacitor has
a first C 2 -terminal connected to the first signal line and
a second C 2 -terminal connected to the fourth gate,
the one of the first source and the first drain is connected to the first signal line,
the other of the first source and the first drain is connected to one of the fourth source and the fourth drain, and
the other of the fourth source and the fourth drain is connected to a third signal line.
4. The display device according to claim 3 , wherein
each of the transfer circuits further comprises
a fifth switch having a fifth gate, a fifth source, and a fifth drain; and
a sixth switch having a sixth gate, a sixth source, and a sixth drain,
the fifth gate is connected to the first gate and one of the sixth source and the sixth drain, and
the sixth gate is connected to the second C 2 -terminal and one of the fifth source and the fifth drain.
5. The display device according to claim 4 , wherein
the one of the sixth source and the sixth drain is connected to the fifth gate, and
the other of the sixth source and the sixth drain of the first transfer circuit is connected to the second signal line.
6. The display device according to claim 4 , wherein
each of the transfer circuits further comprises a seventh switch having a seventh gate, a seventh source, and a seventh drain,
the seventh gate of the first transfer circuit is connected to the output terminal of the second transfer circuit,
the one of the sixth source and the sixth drain is connected to the fifth gate,
one of the seventh source and the seventh drain is connected to the other of the sixth source and the sixth drain, and
the other of the seventh source and the seventh drain is connected to the one of the second source and the second drain.
7. The display device according to claim 1 , wherein
each of the transfer circuits further comprises a third switch having a third gate, a third source, and a third drain,
the one of the first source and the first drain is connected to the first signal line,
one of the third source and the third drain is connected to a third signal line,
the other of the third source and the third drain is connected to the other of the first source and the first drain, and
the third gate connected to a fourth signal line.
8. The display device according to claim 7 , wherein
the first signal line is configured to be supplied with a first signal,
the third signal line is configured to be supplied with a third signal, and
a period in which the first signal line is supplied with the first signal at high level is different from a period in which the third signal line is supplied with the third signal at a high level.
9. The display device according to claim 8 , wherein
the second signal line is supplied with a second signal,
the second signal is maintained at a high level during the first signal and the third signal fall.
10. The display device according to claim 7 , wherein the third signal line is configured to be supplied with a reference potential.
11. The display device according to claim 1 , wherein
the transfer circuits further include a third second transfer circuit,
the gate lines further include a third second gate line,
an output terminal of the third second transfer circuit is connected to the third second gate lines,
the one of the second source and the second drain is connected to the first gate in the third second transfer circuit, and
the other of the second source and the second drain of the third second transfer circuit is connected to the second second gate line.
12. The display device according to claim 1 , further comprising a plurality of pixels, wherein
each of the plurality of pixels include a pixel switch having a gate that is connected to one of the gate lines.
13. The display device according to claim 1 , further comprising a scanning controller, wherein:
the first signal line is a first clock signal line;
the second signal line is a holding potential signal line;
the scanning controller is configured to supply:
a first clock signal to the first transfer circuit and the second transfer circuits through the first clock signal line, and
a holding potential signal to the first transfer circuit through the holding potential signal line, and not to the second transfer circuits; and
in the first transfer circuit, the second gate is connected to the output terminal of the first second transfer circuit, one of the second source and the second drain is connected to the first gate, the other of the second source and the second drain is connected to the holding potential signal line different from the first gate line and the first second-gate line, and the output terminal is connected to the second gate of the second second transfer circuit and the first gate line.
14. The display device according to claim 13 , wherein
the third signal line is a ground terminal line,
the fourth signal line is a second clock signal, and
the scanning controller is configured to further supply a second clock signal to the first transfer circuit and the second transfer circuits through the second clock signal line.
15. A shift register for display device including transfer circuits including a first transfer circuit, and a plurality of second transfer circuits including a first second transfer circuit and a second second transfer circuit, and each connected to one of a plurality of gate lines including a first gate line, a first second gate line, and a second second gate line, the transfer circuits each comprising:
an output terminal;
a first switch having a first gate, a first source, and a first drain, one of the first source and the first drain being connected to a first signal line, and the other of the first source and the first drain being connected to the output terminal; and
a second switch having a second gate, a second source, and a second drain,
wherein:
in the first second transfer circuit,
one of the second source and the second drain is connected to the first gate, and
the output terminal is connected to the first second gate line and the second gate of the first transfer circuit;
in the first transfer circuit,
one of the second source and the second drain is connected to the first gate,
the other of the second source and the second drain is connected to a second signal line different from the first gate line and the first second gate line, and
the output terminal is connected to the second gate of the second transfer circuit and the first gate line; and
in the second second transfer circuit,
one of the second source and the second drain is connected to the first gate,
the other of the second source and the second drain is connected to the first gate line connected to the output terminal of the first transfer circuit, and
the output terminal is connected to the second second gate line.
16. The shift register according to claim 15 , wherein
the one of the first source and the first drain is connected to the first signal line,
each of the transfer circuits further comprises a first capacitor having
a first C 1 -terminal connected to the first gate and
a second C 1 -terminal connected to the other of the first source and the first drain.
17. The shift register according to claim 16 , wherein
each of the transfer circuits further comprises
a second capacitor and
a fourth switch having a fourth gate, a fourth source, and a fourth drain,
the second capacitor has
a first C 2 -terminal connected to the first signal line and
a second C 2 -terminal connected to the fourth gate,
the one of the first source and the first drain is connected to the first signal line,
the other of the first source and the first drain is connected to one of the fourth source and the fourth drain, and
the other of the fourth source and the fourth drain is connected to a third signal line.
18. The shift register according to claim 17 , wherein
each of the transfer circuits further comprises: a fifth switch having a fifth gate, a fifth source, and a fifth drain; and
a sixth switch having a sixth gate, a sixth source, and a sixth drain,
the fifth gate is connected to the first gate and one of the sixth source and the sixth drain, and
the sixth gate is connected to the second C 2 -terminal and one of the fifth source and the fifth drain.