IP Library Granted Patent US 10,242,716
Granted Patent B2
US 10,242,716 · App. 15/448,520 · Granted Mar 26, 2019

Semiconductor device having a slit for aligning a connector and a hole for determining positional accuracy of the slit

Inventor: Naoki Kimura (Ebina Kanagawa, JP)
Assignee: TOSHIBA MEMORY CORPORATION
G11C5/06G11C5/04H01L21/76895H01L22/14H01L23/5386H01L25/0655H01L25/50
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Quick Facts
Patent No.
US 10,242,716
App. No.
15/448,520
Granted
Mar 26, 2019
Kind
B2
Abstract

A semiconductor device includes a substrate, a nonvolatile semiconductor memory disposed on a surface of the substrate, and a controller disposed on a surface of the controller. The substrate has a slit on an edge on which interface connection terminals are formed, a ground pattern, first and second wiring patterns that are electrically connected to the ground pattern and extend in a direction in which the slit extends, and a through hole that is formed between the first and second wiring patterns and is large enough along a dimension between the first and second wiring patterns to span substantially all of the spacing between the first and second wiring patterns.

Claims (35)

1. A semiconductor device comprising:

a substrate;

a nonvolatile semiconductor memory disposed on a surface of the substrate; and

a controller disposed on the surface of the substrate, wherein

the substrate has a slit on an edge at which interface connection terminals are formed, a ground pattern, first and second wiring patterns that are electrically connected to the ground pattern and extend in a direction in which the slit extends, and a through hole that is formed, in a circular shape having a diameter substantially equal to a distance between the first and second wiring pattern, between the first and second wiring patterns.

2. The semiconductor device according to claim 1 , wherein

a distance between the first and second wiring patterns is equal to or greater than a size of the through hole in a direction perpendicular to the direction in which the slit extends.

3. The semiconductor device according to claim 1 , wherein

the through hole is formed at an edge of the substrate opposite to the edge on which the slit is formed.

4. The semiconductor device according to claim 1 , wherein

lengths of the first and second wiring patterns in the direction are longer than the diameter of the through hole.

5. The semiconductor device according to claim 1 , wherein

the substrate also has third and fourth wiring patterns that are electrically connected to the ground pattern and extend in the direction, and a second through hole that is formed, in a circular shape having a diameter substantially equal to a distance between the third and fourth wiring pattern, between the third and fourth wiring patterns.

6. The semiconductor device according to claim 5 , wherein

the through hole and the second through hole are formed at an edge of the substrate opposite to the edge on which the slit is formed.

7. The semiconductor device according to claim 6 , wherein

the through hole and the second through hole are formed at opposite ends of the edge.

8. The semiconductor device according to claim 6 , wherein

a distance between the first and second wiring patterns is substantially the same as a distance between the third and fourth wiring patterns.

9. The semiconductor device according to claim 1 , wherein

the nonvolatile semiconductor memory and the controller are formed on the same surface of the substrate, and the first and second wiring patterns are formed on said same surface.

10. The semiconductor device according to claim 1 , wherein

the first and second wiring patterns are formed as an inner layer of the substrate.

11. The semiconductor device according to claim 1 , further comprising:

a first terminal formed on a surface of the substrate and electrically connected to the first wiring pattern;

a second terminal formed on the surface on which the first terminal is formed and electrically connected to the second wiring pattern; and

a third terminal formed on the surface on which the first terminal is formed and electrically connected to the ground pattern.

12. A computing device comprising:

a power source;

a connector; and

a semiconductor device that is connected to the connector and operates with power supplied from the power source, the semiconductor device including:

a substrate;

a nonvolatile semiconductor memory disposed on a surface of the substrate; and

a controller disposed on the surface of the substrate, wherein

the substrate has a slit on an edge at which interface connection terminals connected to the connector are formed, a ground pattern, first and second wiring patterns that are electrically connected to the ground pattern and extend in a direction in which the slit extends, and a through hole that is formed, in a circular shape having a diameter substantially equal to a distance between the first and second wiring pattern, between the first and second wiring patterns.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 4, 2017
From: KIMURA, NAOKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 042237/0057 →
Priority Claims (1)
JP 2016-191394 · Sep 29, 2016 · national
Continuity (1)
Related Publication 20180090182A1 · Mar 29, 2018