IP Library Granted Patent US 10,303,361
Granted Patent B2
US 10,303,361 · App. 15/448,756 · Granted May 28, 2019

Memory system and method for buffering and storing data

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Quick Facts
Patent No.
US 10,303,361
App. No.
15/448,756
Granted
May 28, 2019
Kind
B2
Abstract

A memory system may include: a memory system may include: a memory device suitable for storing user data and corresponding metadata; and a controller including a memory, the controller being suitable for storing user data and corresponding metadata in the memory and for controlling the memory device for storing therein the user data and the metadata of the memory when sizes of the user data and metadata of the memory reach first and second thresholds, respectively.

Claims (22)

1. A memory system comprising:

a memory device suitable for storing user data and corresponding metadata; and

a controller including a memory, the controller being suitable for storing a user data and a metadata, corresponding to the user data, in the memory, controlling the memory device for storing therein the user data when a size of the user data stored in the memory reaches a first threshold, and controlling the memory device for storing therein the metadata of the memory when a size of the metadata stored in the memory reaches a second threshold,

wherein the controller controls the memory device for storing the user data and the metadata of the memory in two or more different memory blocks of the memory device in an interleaving manner, and

wherein the controller controls the memory device for storing therein the user data and the metadata of the memory when segment numbers of the user data and the metadata reach the first and second thresholds, respectively.

2. The memory system of claim 1 , wherein the controller controls the memory device for storing therein the user data and the metadata of the memory in the interleaving manner on a page basis.

3. The memory system of claim 2 , wherein the controller controls the memory device for storing therein the metadata of the memory by a unit of a page.

4. The memory system of claim 1 , wherein the memory blocks are provided in one or more among a plurality of planes of one or more among a plurality of dies included in the memory device.

5. The memory system of claim 4 , wherein the memory blocks are coupled to a same channel.

6. An operating method of a memory system comprising:

buffering user data and corresponding metadata; and

storing the buffered user data and the buffered metadata,

wherein the storing of the buffered user data and the buffered metadata includes:

controlling the memory device for storing therein the user data when a size of the buffered user data reach a first threshold, and

controlling the memory device for storing therein the metadata of the memory when a size of the metadata stored in the memory reaches a second threshold,

wherein the storing of the buffered user data and the buffered metadata is performed in two or more different memory blocks of the memory system in an interleaving manner, and

wherein the storing of the buffered user data and the buffered metadata is respectively performed when segment numbers of the buffered user data and the buffered metadata reach the first and second thresholds, respectively.

7. The operating method of claim 6 , wherein the storing of the buffered user data and the buffered metadata is performed in the interleaving manner on a page basis.

8. The operating method of claim 7 , wherein the storing of the buffered user data and the buffered metadata includes storing the buffered metadata by a unit of a page.

9. The operating method of claim 6 , wherein the user data are stored in a first super memory block through a first one-shot program.

10. The operating method of claim 9 , wherein then the metadata are stored in a second super memory block through a second one-shot program.

11. The operating method of claim 10 , wherein the first and second super memory blocks are different and the first and second one-shot programs are different.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 3, 2017
From: UM, GI-PYO
To: SK HYNIX INC.
Reel/Frame 041884/0783 →