Memory controller

1. A memory controller that controls a nonvolatile memory including a plurality of physical sectors, each of the plurality of physical sectors including memory cells, the memory controller comprising:

a compression unit that compresses first data;

a data translating unit that performs a first data translation for the compressed first data, and calculates first information based on second data, the second data being a result of the first data translation;

a control unit that determines a first physical sector in which the second data is to be written among the plurality of physical sectors based on the first information and device characteristics of the plurality of the physical sectors; and

a write unit that writes the second data into the first physical sector of the nonvolatile memory, wherein,

in a case where the first information includes capability information of a first rank, the control unit allocates a physical sector having a device characteristic of a second rank to the first physical sector, and

in a case where the first information includes the capability information of a third rank, the control unit allocates a physical sector having a device characteristic of a fourth rank to the first physical sector, the capability information having the first rank and the third rank, the device characteristic having the second rank and the fourth rank, the first rank being higher rank than the third rank, the second rank being lower rank than the fourth rank.

2. The memory controller according to claim 1 , wherein the device characteristic includes information representing degrees of wear of the physical sectors or information representing retention characteristics of the physical sectors.

3. The memory controller according to claim 1 ,

wherein the first data translation is a padding process that includes adding, to the compressed first data, a number of pieces of padding data corresponding to a compression rate of the compressed first data, and

wherein the data translating unit inputs, to the control unit, the first information determined based on the compression rate of the compressed first data and the second data.

4. The memory controller according to claim 1 ,

wherein the first data translation is a logical operation process that includes performing a certain logical operation for the compressed first data and adding identification information representing an execution content of the logical operation to the compressed first data, and

wherein the data translating unit inputs, to the control unit, the first information determined based on the second data.

5. The memory controller according to claim 4 , wherein the logical operation is performed in first management units, the identification information is added in correspondence with data of the first management unit, and the first management unit is controlled to have a different size according to a compression rate of the compressed first data, the first management unit having a certain length acquired by dividing the physical sector into a plurality of parts, and wherein

the data translating unit inputs, to the control unit, the first information determined based on the compression rate of the compressed first data and the second data.

6. The memory controller according to claim 1 , further comprising a garbage collection processing unit that performs a garbage collection including reading data from a first block of the nonvolatile memory and writing the read data into a second block of the nonvolatile memory,

wherein the garbage collection processing unit selects the first block based on the device characteristics of the physical sectors.

7. The memory controller according to claim 1 , further comprising

a device characteristic managing unit that manages device characteristics of the physical sectors, and

a compression/decompression unit that compresses the device characteristics managed by the device characteristic managing unit and stores the compressed device characteristics in a volatile first memory and decompresses a part of the device characteristics stored in the volatile first memory and loads the decompressed device characteristic into the device characteristic managing unit.

8. The memory controller according to claim 1 , further comprising a device characteristic managing unit that manages device characteristics of the physical sectors, wherein the device characteristic managing unit manages the device characteristics of the physical sectors by using a second memory, and the device characteristic managing unit calculates the device characteristics of the physical sectors based on data read from the nonvolatile memory and updates the device characteristics managed by the second memory with the calculated device characteristics of the physical sectors.

9. A memory controller that controls a nonvolatile memory including a plurality of physical sectors, each of the plurality of physical sectors including memory cells, the memory controller comprising:

a compression unit that compresses first data;

a data translating unit that performs a first data translation for the compressed first data, the first data translation being a variable-length error correction code process, the variable-length error correction code process including adding, to the compressed first data, parity having a different parity length according to a compression rate of the compressed first data;

a control unit that determines a first physical sector in which second data is to be written among the plurality of physical sectors based on first information and device characteristics of the plurality of the physical sectors, the second data being a result of the first data translation, the first information being acquired based on the compression rate of the compressed first data; and

a write unit that writes the second data into the first physical sector of the nonvolatile memory, wherein,

in a case where the first information includes capability information of a first rank, the control unit allocates a physical sector having a device characteristic of a second rank to the first physical sector, and

in a case where the first information includes the capability information of a third rank, the control unit allocates a physical sector having a device characteristic of a fourth rank to the first physical sector, the capability information having the first rank and the third rank, the device characteristic having the second rank and the fourth rank, the first rank being higher rank than the third rank, the second rank being lower rank than the fourth rank.

10. The memory controller according to claim 9 , wherein the device characteristic includes information representing degrees of wear of the physical sectors or information representing retention characteristics of the physical sectors.

11. A memory controller that controls a nonvolatile memory including a plurality of physical sectors, each of the plurality of physical sectors including memory cells, the memory controller comprising:

an error predicting unit that predicts a number of bit errors occurring when first data is stored in the plurality of the physical sectors based on the first data to be written into the nonvolatile memory and defective cell information of the plurality of the physical sectors, the defective cell information at least including position information of a defective cell;

a control unit that determines a first physical sector in which the first data is to be written among the plurality of the physical sectors based on the predicted number of bit errors; and

a write unit that writes the first data into the first physical sector of the nonvolatile memory.

12. The memory controller according to claim 11 , wherein the control unit determines a physical sector of which the predicted number of bit errors is minimal as the first physical sector.

13. The memory controller according to claim 11 , further comprising:

a compression unit that compresses the first data; and

a code unit that adds parity of a different parity length in accordance with a compression rate of the compressed first data to the compressed first data,

wherein the error predicting unit predicts a numbers of bit errors occurring when coded first data is stored in the plurality of the physical sectors based on the first data coded by the code unit and the defective cell information of the plurality of the physical sectors, and

wherein the control unit determines a first physical sector in which the first data is to be written among the plurality of the physical sectors based on the predicted numbers of bit errors.

14. The memory controller according to claim 11 , further comprising a retention managing unit that manages retention characteristics of the physical sectors,

wherein the error predicting unit predicts a numbers of bit errors occurring when third data is stored in the plurality of the physical sectors based on the third data to be written into the nonvolatile memory and the retention characteristics of the plurality of the physical sectors, and

wherein the control unit determines a second physical sector in which the third data is to be written among the plurality of the physical sectors based on the predicted numbers of bit errors,

wherein the write unit writes the third data into the second physical sector of the nonvolatile memory.

15. The memory controller according to claim 14 , further comprising a refresh control unit that measures an elapsed time from when the third data is written into the second physical sector and determines timing for moving the third data written into the second physical sector to another physical sector based on a comparison between the measured elapsed time and the retention characteristic of the second physical sector.

16. The memory controller according to claim 11 , further comprising a buffer that stores a plurality of pieces of the first data,

wherein the error predicting unit predicts a numbers of bit errors occurring when the plurality of pieces of the first data are to be stored in the plurality of the physical sectors based on the plurality of pieces of the first data stored in the buffer and the defective cell information of the plurality of the physical sectors, and

wherein the control unit determines a plurality of first physical sectors in which the plurality of pieces of the first data are to be written among the plurality of the physical sectors based on the predicted numbers of bit errors.

17. The memory controller according to claim 11 , further comprising a garbage collection processing unit that performs a garbage collection including reading data from a first block of the nonvolatile memory and writing the read data into a second block of the nonvolatile memory,

wherein the garbage collection processing unit selects the first block based on the defective cell information of the physical sectors.

18. The memory controller according to claim 11 , further comprising

a defective cell managing unit that manages the defective cell information of the physical sectors,

a compression/decompression unit that compresses the defective cell information managed by the defective cell managing unit and stores the compressed defective cell information of the physical sectors in a nonvolatile first memory and decompresses a part of the defective cell information stored in the first memory and loads the decompressed defective cell information into the defective cell managing unit.