IP Library Granted Patent US 9,991,159
Granted Patent B2
US 9,991,159 · App. 15/449,233 · Granted Jun 5, 2018

Semiconductor device manufacture method

Inventors: Fuyuma Ito (Mie, JP); Yasuhito Yoshimizu (Mie, JP); Yuya Akeboshi (Mie, JP); Hisashi Okuchi (Mie, JP); Masayuki Kitamura (Mie, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L21/76879H01L21/0272H01L21/0273H01L21/76802H01L21/76831H01L23/5226H01L23/53238
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Quick Facts
Patent No.
US 9,991,159
App. No.
15/449,233
Granted
Jun 5, 2018
Kind
B2
Abstract

According to some embodiments, a semiconductor device manufacturing method includes forming a sacrificial film on a material film. The method includes processing the sacrificial film, and forming a first groove in the sacrificial film having a first width and a second groove in the sacrificial film having a second width larger than the first width, the material film defining a base of the first groove and a base of the second groove. The method includes forming a catalyst layer on the sacrificial film, and on the base of the first groove and the base of the second groove. The method includes forming a first metal film having a thickness equal to or larger than half the first width and smaller than half the second width on the catalyst layer by plating. The method includes removing at least a portion of the first metal film in the second groove while leaving a portion of the first metal film in the first groove unremoved. The method includes removing the catalyst layer on the sacrificial film while leaving the catalyst layer on the base of the second groove unremoved. The method includes forming a second metal film in the second groove by the plating.

Claims (24)

1. A semiconductor device manufacturing method comprising:

forming a sacrificial film on a material film;

processing the sacrificial film, and forming a first groove in the sacrificial film having a first width and a second groove in the sacrificial film having a second width larger than the first width, the material film defining a base of the first groove and a base of the second groove;

forming a catalyst layer on the sacrificial film, and on the base of the first groove and the base of the second groove;

forming a first metal film having a thickness equal to or larger than half the first width, and smaller than half the second width, on the catalyst layer by plating;

removing at least a portion of the first metal film in the second groove while leaving at least a portion of the first metal film in the first groove unremoved;

removing the catalyst layer on the sacrificial film while leaving the catalyst layer on the base of the second groove unremoved; and

forming a second metal film in the second groove by plating.

2. The semiconductor device manufacturing method according to claim 1 ,

wherein the catalyst layer includes at least one of palladium, cobalt, or platinum,

the first metal film includes nickel, and

the second metal film includes copper.

3. The semiconductor device manufacturing method according to claim 1 ,

wherein the first and second metal films are formed by electroless plating using the catalyst layer.

4. The semiconductor device manufacturing method according to claim 1 , further comprising:

after forming the second metal film, removing the sacrificial film; and

forming a covering film on side surfaces of the first metal film and second metal film.

5. The semiconductor device manufacturing method according to claim 4 , further comprising

forming an organic molecular film on the sacrificial film and on the material film before forming the catalyst layer.

6. The semiconductor device manufacturing method according to claim 5 , wherein the organic molecular film is a self-assembled monolayer film.

7. The semiconductor device manufacturing method according to claim 4 ,

wherein the material film and the covering film each includes a silicon nitride film.

8. The semiconductor device manufacturing method according to claim 1 ,

wherein the sacrificial film is a photoresist film.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 21, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043063/0178 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 13, 2017
From: ITO, FUYUMA; YOSHIMIZU, YASUHITO; AKEBOSHI, YUYA; OKUCHI, HISASHI; KITAMURA, MASAYUKI
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 042003/0480 →
Priority Claims (1)
JP 2016-184585 · Sep 21, 2016 · national
Continuity (1)
Related Publication 20180082893A1 · Mar 22, 2018