IP Library Granted Patent US 9,871,583
Granted Patent B1
US 9,871,583 · App. 15/449,884 · Granted Jan 16, 2018

Channel diagnostics based on equalizer coefficients

Inventors: Shih Cheng Wang (Pensacola Beach, FL); Seyedmohammadreza Motaghiannezam (Los Altos, CA); Matthew C. Bashaw (Palo Alto, CA)
Assignee: INPHI CORPORATION
H04B10/0795H04B10/25073H04B10/614H04L25/03019
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Quick Facts
Patent No.
US 9,871,583
App. No.
15/449,884
Granted
Jan 16, 2018
Kind
B1
Abstract

A receiver applies a calibration method to compensate for skew between input channels. The receiver skew is estimated by observing the coefficients of an adaptive equalizer which adjusts the coefficients based on time-varying properties of the multi-channel input signal. The receiver skew is compensated by programming the phase of the sampling clocks for the different channels. Furthermore, during real-time operation of the receiver, channel diagnostics is performed to automatically estimate differential group delay and/or other channel characteristics based on the equalizer coefficients using a frequency averaging or polarization averaging approach. Framer information can furthermore be utilized to estimate differential group delay that is an integer multiple of the symbol rate. Additionally, a DSP reset may be performed when substantial signal degradation is detected based on the channel diagnostics information.

Claims (50)

1. A device for generating channel diagnostics information in a communication system, comprising:

a digital signal processor including an adaptive equalizer to equalize a digital signal vector having a time-varying range of polarization states, the adaptive equalizer to adaptively generate equalizer coefficients based on characteristics of the digital signal vector and to generate an equalized signal vector;

a demodulator to demodulate the equalized signal vector to generate a demodulated signal;

a decoder to decode the demodulated signal to generate a decoded signal;

a channel diagnostics block to obtain the equalizer coefficients of the adaptive equalizer generated over the range of polarization states of the digital signal vector, to determine an estimated frequency response of the adaptive equalizer from the equalizer coefficients, and to determine an average differential group delay in the digital signal vector over the range of polarization states based on the estimated frequency response.

2. The device of claim 1 , further comprising:

a framer to format the decoded signal for interfacing to a host interface, the framer to detect equalizer-induced differential group delay in the decoded signal introduced by the adaptive equalizer; and

wherein the channel diagnostics block is further configured to adjust the average differential group delay based on the equalizer-induced differential group delay to generate a compensated differential group delay.

3. The device of claim 2 , wherein the equalizer-induced differential group delay comprises an integer number of symbol periods.

4. The device of claim 2 , wherein the framer comprises a register storing the detected equalizer-induced differential group delay and wherein the channel diagnostics block is configured to read the register to obtain the detected equalizer-induced differential group delay.

5. The device of claim 1 , wherein the channel diagnostics block is configured to determine the average group delay by approximating the adaptive equalizer as a plurality of windowed fractional delay filters, determining fraction group delays of frequency responses corresponding to each of the windowed fractional delay filters, and averaging the fractional group delays to determine the average group delay.

6. The device of claim 1 wherein the adaptive equalizer is embodied in a digital signal processor, and wherein the channel diagnostics block is embodied in an external processor separate from the digital signal processor, the external processor coupled to the digital signal processor to receive the equalizer coefficients.

7. The device of claim 1 wherein the channel diagnostics block is embodied in a digital signal processor.

8. The device of claim 1 , wherein the digital signal processor comprises:

a matrix rotator to receive an input signal vector and to apply a time-varying rotation to the input signal vector to generate the digital signal vector.

9. A system for generating channel diagnostics information, comprising:

an optical front end to receive an optical signal and convert to the optical signal to an analog signal vector;

an analog front end to sample the analog signal vector based on a sampling clock to generate a digital signal vector;

a digital signal processor including an adaptive equalizer to equalize a digital signal vector having a time-varying range of polarization states, the adaptive equalizer to adaptively generate equalizer coefficients based on characteristics of the digital signal vector and to generate an equalized signal vector;

a demodulator to demodulate the equalized signal vector to generate a demodulated signal;

a decoder to decode the demodulated signal to generate a decoded signal;

a channel diagnostics block to obtain the equalizer coefficients of the adaptive equalizer generated over the range of polarization states of the digital signal vector, to determine an estimated frequency response of the adaptive equalizer from the equalizer coefficients, and to determine an average differential group delay in the digital signal vector over the range of polarization states based on the estimated frequency response.

10. The system of claim 9 , further comprising:

a framer to format the decoded signal for interfacing to a host interface, the framer to detect equalizer-induced differential group delay in the decoded signal introduced by the adaptive equalizer; and

wherein the channel diagnostics block is further configured to adjust the average differential group delay based on the equalizer-induced differential group delay to generate a compensated differential group delay.

11. The system of claim 10 , wherein the equalizer-induced differential group delay comprises an integer number of symbol periods.

12. The system of claim 10 , wherein the framer comprises a register storing the detected equalizer-induced differential group delay and wherein the channel diagnostics block is configured to read the register to obtain the detected equalizer-induced differential group delay.

13. The system of claim 10 , wherein the channel diagnostics block is configured to determine the average group delay by approximating the adaptive equalizer as a plurality of windowed fractional delay filters, determining fraction group delays of frequency responses corresponding to each of the windowed fractional delay filters, and averaging the fractional group delays to determine the average group delay.

14. The system of claim 10 , wherein the analog front end comprises:

an analog-to-digital converter to convert an analog signal vector to the digital signal vector, the analog signal vector having a plurality of channels, the analog-to-digital converter sampling each of the plurality of channels based on a corresponding sampling clock;

a skew compensation block to generate the corresponding sampling clocks for each of the plurality of channels based on skew compensation values specifying an amount of skew compensation for each of the plurality of channels; and

a skew estimator to obtain the coefficients of the adaptive equalizer and determine an amount of skew between at least two of the plurality of channels based on the average differential group delay, and to program the skew compensation block with the skew compensation values based on the determined amount of skew.

15. The system of claim 10 wherein the adaptive equalizer is embodied in a digital signal processor, and wherein the channel diagnostics block is embodied in an external processor separate from the digital signal processor, the external processor coupled to the digital signal processor to receive the equalizer coefficients.

16. The system of claim 10 wherein the channel diagnostics block is embodied in a digital signal processor.

17. The system of claim 10 , wherein the digital signal processor comprises:

a matrix rotator to receive an input signal vector and to apply a time-varying rotation to the input signal vector to generate the digital signal vector.

18. The system of claim 10 , wherein the optical front end comprises:

a polarization scrambler to modify a polarization state of the optical signal over a time range to generate a polarization-scrambled optical signal; and

an optical-to-electrical converter to convert the polarization-scrambled optical signal to the analog signal vector.

19. A method for generating channel diagnostics information in a communication system, the method comprising:

receiving a digital signal vector having a time-varying range of polarization states;

equalizing the digital signal vector using an adaptive equalizer to generate an equalized signal vector, the adaptive equalizer adaptively generate equalizer coefficients based on characteristics of the digital signal vector;

demodulating the equalized signal vector to generate a demodulated signal;

decoding the demodulated signal to generate a decoded signal;

determining an estimated frequency response of the adaptive equalizer over the range of polarization states based on the equalizer coefficients; and

determining an average differential group delay over the range of polarizations states based on the estimated frequency response.

20. The method of claim 19 , further comprising:

formatting, by a framer, the decoded signal for interfacing to a host interface;

detecting, by the framer, equalizer-induced differential group delay in the decoded signal introduced by the adaptive equalizer;

adjusting the average differential group delay based on the equalizer-induced differential group delay to generate a compensated differential group delay.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 24, 2017
From: CLARIPHY COMMUNICATIONS, INC.
To: INPHI CORPORATION
Reel/Frame 042492/0789 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2017
From: WANG, SHIH CHENG; MOTAGHIANNEZAM, SEYEDMOHAMMADREZA; BASHAW, MATTHEW C.
To: CLARIPHY COMMUNICATIONS, INC.
Reel/Frame 041524/0305 →
Continuity (7)
Continuation 14798083 · Jul 13, 2015
Continuation 13744211 · Jan 17, 2013
Provisional Application 61587572 · Jan 17, 2012
Provisional Application 61677460 · Jul 30, 2012
Provisional Application 61683169 · Aug 14, 2012
Provisional Application 61704490 · Sep 22, 2012
Provisional Application 61745389 · Dec 21, 2012