IP Library Granted Patent US 9,875,851
Granted Patent B2
US 9,875,851 · App. 15/451,120 · Granted Jan 23, 2018

Ceramic multi-layered capacitor

Inventors: Guenter Engel (Leibnitz, AT); Michael Schossmann (Deutschlandsberg, AT); Markus Koini (Seiersberg, AT); Andrea Testino (Wuerenlingen, CH); Christian Hoffmann (Munich, DE)
Assignee: EPCOS AG
H01G4/30B32B18/00C04B35/493H01G4/008H01G4/012H01G4/1218H01G4/1236H01G4/232H01G4/248B32B2457/00C04B2235/3203C04B2235/3234C04B2235/3249C04B2235/3274C04B2235/3296C04B2235/3427C04B2235/768C04B2235/79C04B2237/348C04B2237/704
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Quick Facts
Patent No.
US 9,875,851
App. No.
15/451,120
Granted
Jan 23, 2018
Kind
B2
Abstract

A ceramic multi-layer capacitor includes a main body, which has ceramic layers arranged along a layer stacking direction to form a stack, and first and second electrode layers arranged between the ceramic layers. The multi-layer capacitor also includes a first external contact-connection arranged on a first side surface of the main body and electrically conductively connected to the first electrode layers, and a second external contact-connection arranged on a second side surface of the main body. The second side surface is situated opposite the first side surface and is electrically conductively connected to the second electrode layers.

Claims (47)

1. A ceramic multi-layer capacitor comprising:

a main body including ceramic layers arranged along a layer stacking direction to form a stack, the main body further including first and second electrode layers arranged between the ceramic layers, wherein each of the ceramic layers comprise a ceramic material which is an antiferroelectric dielectric;

a first external contact-connection arranged on a first side surface of the main body and electrically conductively connected to the first electrode layers; and

a second external contact-connection arranged on a second side surface of the main body, the second side surface located opposite the first side surface and being electrically conductively connected to the second electrode layers,

wherein the main body has a width B along the layer stacking direction,

wherein the main body has a height H perpendicular to the first side surface,

wherein the main body has a length L perpendicular to the height H and perpendicular to the layer stacking direction,

wherein B/H≧0.2 holds true, and

wherein a ratio between the width B, the height H and the length L is such that a ratio of a feed cross section of the electrode layers to a useful cross section of the electrode layers results in an ESR value of the multi-layer capacitor between 3 mΩ and 5 mΩ during operation with a frequency between too kHz and 1 MHz.

2. The multi-layer capacitor according to claim 1 , wherein L/B≧1 holds true.

3. The multi-layer capacitor according to claim 1 , wherein L/H≧1 holds true.

4. The multi-layer capacitor according to claim 1 , wherein the main body has third electrode layers that are each floating electrodes and that are each electrically conductively isolated from external contact connections.

5. The multi-layer capacitor according to claim 4 , wherein the third electrode layers overlap the first and second electrode layers.

6. The multi-layer capacitor according to claim 1 , wherein each ceramic layer has a layer thickness of between 3 μm and 200 μm.

7. The multi-layer capacitor according to claim 1 , wherein each first electrode layer has a layer thickness of between 0.1 μm and 10 μm and wherein each second electrode layer has a layer thickness of between 0.1 μm and 10 μm.

8. The multi-layer capacitor according to claim 1 , wherein the main body has at least 10 first electrode layers and at least 10 second electrode layers.

9. The multi-layer capacitor according to claim 1 , wherein the following relationship holds true:

number of first electrode layers/width B≧10/mm.

10. The multi-layer capacitor according to claim 1 , wherein the first and second electrode layers comprise copper.

11. The multi-layer capacitor according to claim 1 , wherein the first and second side surfaces are surface-treated.

12. The multi-layer capacitor according to claim 11 , wherein the first and second side surfaces are lapped, ground or plasma-etched.

13. The multi-layer capacitor according to claim 1 , wherein the first and second external contact-connections each have at least one sputtering layer in direct contact with the first or second electrode layers.

14. The multi-layer capacitor according to claim 1 , wherein the ceramic layers comprise a ceramic material for which the following formula holds true:

Pb (1−1.5a−0.5b+1.5d+e+0.5f) A a B b (Zr 1−X Ti X ) 1−c−d−e−f Li d C e Fe f Si c O 3 +y·PbO  (I)

wherein

A is selected from the group consisting of La, Nd, Y, Eu, Gd, Tb, Dy, Ho, Er and Yb;

B is selected from the group consisting of Na, K and Ag;

C is selected from the group consisting of Ni, Cu, Co and Mn; and

0<a<0.12

0.05≦x≦0.3

0≦b≦0.12

0≦c≦0.12

0≦d≦0.12

0≦e≦0.12

0≦f≦0.12

0≦y≦1, and

b+d+e+f>0.

15. A ceramic multi-layer capacitor comprising:

a main body including ceramic layers arranged along a layer stacking direction to form a stack, the main body further including first and second electrode layers arranged between the ceramic layers;

a first external contact-connection arranged on a first side surface of the main body and electrically conductively connected to the first electrode layers; and

a second external contact-connection arranged on a second side surface of the main body, the second side surface located opposite the first side surface and being electrically conductively connected to the second electrode layers,

wherein the main body has a width B along the layer stacking direction,

wherein the main body has a height H perpendicular to the first side surface,

wherein the main body has a length L perpendicular to the height H and perpendicular to the layer stacking direction,

wherein B/H≧0.2 holds true,

wherein the main body has third electrode layers that are each floating electrodes and that are each electrically conductively isolated from external contact connections, and

wherein a layer thickness of the ceramic layers is so small that the multi-layer capacitor has an ESR value between 3 mΩ and 5 mΩ during operation with a frequency between 100 kHz and 1 MHz.

Assignments (1)
CHANGE OF NAME Recorded Mar 15, 2023
From: EPCOS AG
To: TDK ELECTRONICS AG
Reel/Frame 063101/0709 →
Continuity (2)
Continuation 14399860
Related Publication 20170178815A1 · Jun 22, 2017