Non-volatile semiconductor memory device
According to one embodiment, a non-volatile semiconductor memory device is disclosed. The device includes a semiconductor substrate, and a memory cell array provided on the semiconductor substrate. The memory cell array includes a plurality of memory transistors which are electrically rewritable and arranged in a three-dimensional manner. The device further includes a latch provided above the semiconductor substrate and configured to hold data that is to be written in the memory cell array. The latch includes a capacitor and a first field-effect transistor which is connected to the capacitor and includes a first oxide semiconductor layer.
1. A non-volatile semiconductor memory device comprising:
a semiconductor substrate;
a memory cell array provided on the semiconductor substrate, and comprising a plurality of memory transistors, the plurality of memory transistors being electrically rewritable and arranged in a three-dimensional manner; and
a latch provided above the semiconductor substrate and configured to hold data that is to be written in the memory cell array, and the latch comprising a capacitor and a first field- effect transistor which is connected to the capacitor and comprises a first oxide semiconductor layer, and a second field-effect transistor which is connected to the capacitor and comprises a second oxide semiconductor layer.
2. The device of claim 1 , wherein the first field-effect transistor further comprises:
a pair of first source/drain regions provided in the first oxide semiconductor layer, and
a channel region provided between the pair of first source/drain regions, and having a conductivity type that is same as a conductivity type of the pair of first source/drain regions.
3. The device of claim 1 , wherein the second field-effect transistor further comprises:
a pair of second source/drain regions provided in the second oxide semiconductor layer, and
a channel region provided between the pair of second source/drain regions, and having a conductivity type that is same as a conductive type of the pair of second source/drain regions.
4. The device of claim 1 , wherein the first field-effect transistor and the second field-effect transistor are connected in series, and the capacitor is connected to a connection node of the first field-effect transistor and the second field-effect transistor.
5. The device of claim 1 , wherein the first field-effect transistor and the second field-effect transistor each further comprises a gate electrode which contains copper, tantalum nitride, titanium nitride, tungsten nitride, tantalum, titanium, tungsten, aluminum or molybdenum, or alloy of tantalum, titanium, tungsten, aluminum or molybdenum.
6. The device of claim 1 , wherein the oxide semiconductor layer contains InGaZnO, InSnZnO, InGaSnZnO, InGaSnO, AlInGaZnO, AlInSnZnO, In 2 O 3 , Ga 2 O 3 , TiO 2 , ZnO, or SnO 2 .
7. The device of claim 1 , wherein the second oxide semiconductor layer contains InGaZnO, InSnZnO, InGaSnZnO, InGaSnO, AlInGaZnO, AlInSnZnO, In 2 O 3 , Ga 2 O 3 , TiO 2 , ZnO, or SnO 2 .
8. The device of claim 1 , wherein the latch constitutes a page buffer.
9. The device of claim 4 , further comprises a sense amplifier and a bit line, wherein the first field-effect transistor of the latch is connected to the sense amplifier, and the second field-effect transistor of the latch is connected to the bit line.
10. The device of claim 9 , wherein the latch is disposed lower than the bit line.
11. The device of claim 9 , wherein the latch is disposed higher than the bit line.
12. The device of claim 1 , further comprising a stair-like step portion including a plurality of steps provided around the memory cell array, wherein the stair-like step portion including a first stair-like step portion including a plurality of steps, and the latch is disposed on the first stair-like step portion.
13. The device of claim 12 , wherein the plurality of steps of the first stair-like step portion are arranged along a direction perpendicular to a longitudinal direction of the bit line as viewed from above.
14. The device of claim 12 , wherein the stair-like step portion further includes a second stair-like step portion including a plurality of steps.
15. The device of claim 14 , wherein the plurality of steps of the second stair-like step portion are arranged along the longitudinal direction of the bit line as viewed from above.
16. The device of claim 14 , further comprising a plug connected to a conductive layer constituting one of the plurality of steps of the second stair-like step portion.
17. The device of claim 1 , wherein the latch is disposed above a surface of the semiconductor outside the memory cell array.
18. The device of claim 1 , wherein the plurality of memory transistors are connected in series.