IP Library Granted Patent US 10,291,261
Granted Patent B2
US 10,291,261 · App. 15/453,126 · Granted May 14, 2019

Early selection decoding and automatic tuning

Inventors: Johnson Yen (Fremont, CA); HongChich Chou (Milpitas, CA); Yi-Min Lin (San Jose, CA)
Assignee: SK Hynix Inc.
H03M13/3715
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Quick Facts
Patent No.
US 10,291,261
App. No.
15/453,126
Granted
May 14, 2019
Kind
B2
Abstract

Techniques are described for codeword decoding. In an example, a system computes a checksum for a codeword based on the codeword and a parity check matrix. The system compares the checksum to thresholds. Each threshold is associated with a different decoder from a plurality of decoders available on the system. The system selects a decoder from the plurality of decoders. The decoder is selected based on the comparison of the checksum to the thresholds. The system decodes the codeword by using the selected decoder.

Claims (43)

1. A computer-implemented method for codeword decoding on a system, the computer-implemented method comprising:

computing a checksum for a codeword based on the codeword and a parity check matrix;

comparing the checksum to thresholds, wherein each threshold is associated with a different decoder from a plurality of decoders available on the system;

selecting a decoder from the plurality of decoders, wherein the decoder is selected based on the comparison of the checksum to the thresholds; and

decoding the codeword by using the decoder, wherein:

a threshold associated with the decoder is updated based on a comparison between an observed performance and an expected performance, wherein each of the observed performance and expected performance comprises at least of a bit error rate, a number of decoding failures, a decoding latency, or a power consumption,

the observed performance is computed based on the decoding of the codeword, and

the threshold is decreased based on the comparison indicating that the observed performance is worse than the expected performance.

2. The computer-implemented method of claim 1 , wherein the checksum comprises a count of unsatisfied check nodes based on the parity check matrix.

3. The computer-implemented method of claim 1 , wherein computing the checksum comprises applying a checksum function, and wherein the checksum function comprises a product of the codeword and a transpose of the parity check matrix.

4. The computer-implemented method of claim 1 , wherein each of the plurality of decoders implements a unique decoding scheme that is associated with a decoding latency and a bit error rate, and wherein the decoder is selected based on a rule that specifies that, the higher the checksum is, a selection is for a higher decoding latency, lower bit error rate decoding scheme.

5. The computer-implemented method of claim 1 , wherein the plurality of decoders comprise a one-read bit flipping decoder, a one-read min-sum hard decoder, a two-read min-sum soft decoder, and a multiple-read min-sum soft-decoder.

6. The computer-implemented method of claim 5 , wherein the one-read bit flipping decoder is selected based on the checksum having a value smaller than 750.

7. The computer-implemented method of claim 5 , wherein the one-read min-sum hard decoder is selected based on the checksum having a value between 750 and 1,150.

8. The computer-implemented method of claim 5 , wherein the two-read min-sum soft decoder is selected based on the checksum having a value between 1,150 and 1,400.

9. The computer-implemented method of claim 5 , wherein the multiple-read min-sum soft decoder is selected based on the checksum having a value larger than 1,400.

10. A system comprising:

a plurality of decoders;

one or more processors; and

one or more memories communicatively coupled with the one or more processors and storing instructions that, upon execution by the one or more processors, configure the system to at least:

classify a codeword based on a checksum associated with the codeword and based on thresholds associated with the plurality of decoders;

select a decoder from the plurality of decoders based on the classification of the codeword; and

decode the codeword by using the decoder, wherein:

a threshold associated with the decoder is updated based on a comparison between an observed performance and an expected performance, wherein each of the observed performance and expected performance comprises at least of a bit error rate, a number of decoding failures, a decoding latency, or a power consumption,

the observed performance is computed based on the decoding of the codeword, and

the threshold is decreased based on the comparison indicating that the observed performance is worse than the expected performance.

11. The system of claim 10 , wherein the checksum is computed based on the codeword and a parity check matrix, and wherein each threshold is associated with a different decoder from the plurality of decoders.

12. The system of claim 10 , wherein classifying the codeword comprises comparing the checksum to the thresholds, and wherein the decoder is selected based on the comparison of the checksum to the thresholds.

13. The system of claim 10 , wherein the thresholds are set based on a simulation of codeword decoding and measured latencies and bit error rates.

14. The system of claim 10 , wherein the threshold associated with the decoder is set based on a decoding scheme unique to the decoder.

15. The system of claim 14 , wherein the threshold is set based on the decoding latency and the bit error rate of the decoding scheme.

16. One or more non-transitory computer-readable storage media comprising instructions that, upon execution on a system, configure the system to perform operations comprising:

computing a checksum for a codeword based on the codeword and a parity check matrix;

comparing the checksum to thresholds, wherein each threshold is associated with a different decoder from a plurality of decoders of the system;

selecting a decoder from the plurality of decoders, wherein the decoder is selected based on the comparison of the checksum to the thresholds; and

decoding the codeword by using the decoder, wherein:

a threshold associated with the decoder is updated based on a comparison between an observed performance and an expected performance, wherein each of the observed performance and expected performance comprises at least of a bit error rate, a number of decoding failures, a decoding latency, or a power consumption,

the observed performance is computed based on the decoding of the codeword, and

the threshold is decreased based on the comparison indicating that the observed performance is worse than the expected performance.

17. The one or more non-transitory computer-readable storage media of claim 16 , wherein the thresholds are updated over time based on the decoding of the codeword.

18. The one or more non-transitory computer-readable storage media of claim 16 , wherein the threshold associated with the decoder is updated based on a comparison between an observed bit error rate and an expected bit error rate, wherein the observed bit error rate is computed based on the decoding of the codeword, and wherein the threshold is decreased based on the comparison of the observed bit error rate and the expected bit error rate indicating that the observed bit error rate is higher than the expected bit error rate.

19. The one or more non-transitory computer-readable storage media of claim 16 , wherein the threshold associated with the decoder is updated based on tracking the number of decoding failures of the decoder and comparing the number to a fail threshold.

20. The one or more non-transitory computer-readable storage media of claim 19 , wherein the tacking is repeated for a predefined number of codewords that are decoded with the decoder, and wherein the threshold is decreased based on the number of decoding failures being greater than the fail threshold after decoding the predefined number of codewords.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2017
From: SK HYNIX MEMORY SOLUTIONS INC.
To: SK HYNIX INC.
Reel/Frame 043389/0705 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2017
From: YEN, JOHNSON; CHOU, HONGCHICH; LIN, YI-MIN
To: SK HYNIX MEMORY SOLUTIONS INC.
Reel/Frame 043347/0986 →
Continuity (2)
Provisional Application 62327319 · Apr 25, 2016
Related Publication 20170310342A1 · Oct 26, 2017
Cited By (2)
US 12,200,183 US 12,659,075