IP Library Granted Patent US 10,243,725
Granted Patent B2
US 10,243,725 · App. 15/454,245 · Granted Mar 26, 2019

Apparatus and method for generating transmitting sequence, training sequence synchronization apparatus and method, apparatus and method for estimating channel spacing and system

Inventors: Ying Zhao (Beijing, CN); Liang Dou (Beijing, CN); Zhenning Tao (Beijing, CN)
Assignee: FUJITSU LIMITED
H04L7/041H04B10/00H04L7/0041H04L7/0087H04L7/10
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Quick Facts
Patent No.
US 10,243,725
App. No.
15/454,245
Granted
Mar 26, 2019
Kind
B2
Abstract

Embodiments of this disclosure provide an apparatus and method for generating a transmitting sequence, a training sequence synchronization apparatus and method, an apparatus and method for estimating channel spacing and a system. The training sequence synchronization apparatus includes: a delay correlation processing unit configured to parallelly perform autocorrelation operations of different delay amounts on a receiving sequence containing a periodic training sequence to obtain multiple parallel correlation sequences; a superimposition processing unit configured to perform a superimposition operation on the multiple parallel correlation sequences to obtain a synchronization correlation sequence; and a synchronization extracting unit configured to perform a synchronization position extraction on the synchronization correlation sequence to obtain a synchronization position of the training sequence. With the embodiments of this disclosure, anti-noise performance of the training sequence may be enhanced.

Claims (28)

1. A training sequence synchronization apparatus, comprising:

a memory that stores a plurality of instructions; and

a processor coupled to the memory and configured to execute the instructions to:

parallelly perform autocorrelation operations of different delay amounts on a receiving sequence containing a periodic training sequence to obtain multiple parallel correlation sequences;

perform a superimposition operation on the multiple parallel correlation sequences to obtain a synchronization correlation sequence; and

perform a synchronization position extraction on the synchronization correlation sequence to obtain a synchronization position of the training sequence,

wherein the different delay amounts are integral multiples of a period of the training sequence, respectively.

2. The apparatus according to claim 1 , wherein the processor is configured to execute the instructions to add up amplitudes of the multiple parallel correlation sequences to obtain a single sequence as the synchronization correlation sequence.

3. The apparatus according to claim 1 , wherein to perform the superimposition operation, the processor is configured to execute the instructions to:

perform a complex conjugate multiplication on two neighboring correlation sequences in the multiple parallel correlation sequences; and

add up all values, obtained by performing the complex conjugate multiplication on the two neighboring correlation sequences in the multiple parallel correlation sequences, to obtain a single sequence as the synchronization correlation sequence.

4. The apparatus according to claim 1 , wherein the processor is configured to execute the instructions to take a maximum value of the synchronization correlation sequence as the synchronization position of the training sequence.

5. The apparatus according to claim 1 , wherein the processor is configured to execute the instructions to take a center of gravity of all values within a predetermined range of a maximum value of the synchronization correlation sequence as the synchronization position of the training sequence.

6. The apparatus according to claim 1 , wherein the processor is further configured to execute the instructions to:

preprocess the receiving sequence containing the periodic training sequence to obtain the preprocessed receiving sequence.

7. The apparatus according to claim 1 , wherein the periodic training sequence comprises multiple repeated sub-sequences, the sub-sequences being connected to each other in an end-to-end manner to constitute the periodic training sequence.

8. The apparatus according to claim 1 , wherein the periodic training sequence is a part of or all of whole training sequence.

9. An apparatus for estimating a channel spacing, comprising:

a memory that stores a plurality of instructions; and

a processor coupled to the memory and configured to execute the instructions to:

parallelly perform autocorrelation operations of different delay amounts on a receiving sequence of a center channel containing a periodic first training sequence to obtain multiple parallel first correlation sequences;

perform a superimposition operation on the multiple parallel first correlation sequences to obtain a first synchronization correlation sequence;

perform a synchronization position extraction on the first synchronization correlation sequence to obtain a synchronization position of the first training sequence of the center channel;

parallelly perform autocorrelation operations of different delay amounts on a receiving sequence of a neighboring channel containing a periodic second training sequence to obtain multiple parallel second correlation sequences;

perform a superimposition operation on the multiple parallel second correlation sequences to obtain a second synchronization correlation sequence;

perform a synchronization position extraction on the second synchronization correlation sequence to obtain a synchronization position of the second training sequence of the neighboring channel;

estimate a frequency offset of the center channel by using the synchronization position of the first training sequence of the center channel, and estimate a frequency offset of the neighboring channel by using the synchronization position of the second training sequence of the neighboring channel; and

estimate the channel spacing by using the frequency offset of the center channel and the frequency offset of the neighboring channel.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 13, 2025
From: FUJITSU LIMITED
To: 1FINITY INC.
Reel/Frame 072423/0322 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2017
From: ZHAO, YING; DOU, LIANG; TAO, ZHENNING
To: FUJITSU LIMITED
Reel/Frame 041554/0081 →
Priority Claims (1)
CN 2016 1 0157773 · Mar 18, 2016 · national
Continuity (1)
Related Publication 20170272232A1 · Sep 21, 2017
Cited By (1)
US 12,241,368