Signal receiving circuit and method, and signal detecting circuit
This document discusses, among other things, a signal receiving circuit, configured to receive an input voltage signal. The signal receiving circuit can comprise an input voltage regulating circuit and a comparing circuit. The input voltage regulating circuit can carry out a waveform pre-regulation for the input voltage signal to obtain a first voltage signal, and the comparing circuit can compare the first voltage signal with a second voltage signal, and output a comparison voltage signal having a pulse width that satisfies a first predetermined condition indicative that the input voltage signal is correctly identifiable. The present document further discusses a signal detecting circuit and a signal receiving method.
1. A system, comprising:
a signal receiving circuit configured to receive an input voltage signal, the input voltage signal including a plurality of pulses, the plurality of pulses including a first pulse and a second pulse separate from the first pulse, the signal receiving circuit including a biphase mark coding (BMC) receiver, the signal receiving circuit including:
an input voltage regulating circuit configured to modify a shape of the first pulse and the second pulse to obtain a regulated voltage signal; and
a comparing circuit configured to compare the regulated voltage signal with a reference voltage signal and detect received data in the input voltage signal in response to the comparison,
the comparing circuit configured to generate a comparison voltage signal having a pulse width that satisfies a predetermined condition in response to the comparison and the input voltage regulating circuit configured to obtain the regulated voltage signal in response to the comparison voltage signal.
2. The system of claim 1 , wherein the comparing circuit includes a positive input terminal configured to receive the regulated voltage signal, and a negative input terminal configured to receive the reference voltage signal,
wherein the input voltage regulating circuit includes an alternating current coupling circuit configured to provide alternating current coupling to the input voltage signal.
3. The system of claim 1 , wherein the comparing circuit includes a negative input terminal configured to receive the regulated voltage signal, and a positive input terminal configured to receive the reference voltage signal,
wherein the input voltage regulating circuit includes a filtering circuit configured to filter the input voltage signal.
4. The system of claim 1 , comprising:
a digital detecting circuit configured to detect that the input voltage signal is a BMC data signal based on the comparison voltage signal.
5. A system, comprising:
means for receiving an input voltage signal, the input voltage signal including a plurality of pulses, the plurality of pulses including a first pulse and a second pulse separate from the first pulse, the means for receiving the input voltage signal including a bi-phase mark coding (BMC) receiver;
means for modifying a shape of the first pulse and the second pulse to obtain a regulated voltage signal; and
means for comparing the regulated voltage signal with a reference voltage signal and detecting received data in the input voltage signal in response to the comparison, and generating a comparison voltage signal having a pulse width that satisfies a predetermined condition in response to the comparison, wherein the means for modifying obtains the regulated voltage signal in response to the comparison voltage signal.
6. The system of claim 5 , wherein the means for modifying include means for providing alternating current coupling to the input voltage signal.
7. The system of claim 5 , wherein the means for modifying include means for filtering the input voltage signal.
8. The system of claim 5 , wherein the means for comparing include a comparing circuit, the comparing circuit includes a positive input terminal configured to receive the regulated voltage signal, and a negative input terminal configured to receive the reference voltage signal,
wherein the means for modifying include an alternating current coupling circuit configured to provide alternating current coupling to the input voltage signal.
9. The system of claim 5 , wherein the means for comparing include a comparing circuit, the comparing circuit includes a negative input terminal configured to receive the regulated voltage signal, and a positive input terminal configured to receive the reference voltage signal,
wherein the means for modifying include a filtering circuit configured to filter the input voltage signal.
10. A method, comprising:
receiving an input voltage signal at a signal receiving circuit, the input voltage signal including a plurality of pulses, the plurality of pulses including a first pulse and a second pulse separate from the first pulse, the signal receiving circuit including an input voltage regulating circuit and a comparing circuit;
modifying a shape of the first pulse and the second pulse of the input voltage signal to obtain a regulated voltage signal using the input voltage regulating circuit;
comparing the regulated voltage signal with a reference voltage signal using the comparing circuit and detecting received data in the input voltage signal in response to the comparison;
generating a comparison voltage signal having a pulse width that satisfies a predetermined condition in response to the comparison and obtaining the regulated voltage signal in response to the comparison voltage signal; and
detecting that the input voltage signal is a biphase mark coding (BMC) data signal based on the comparison voltage signal.
11. The method of claim 10 ,
wherein the input voltage regulating circuit includes an alternating current coupling circuit, and the modifying includes providing alternating current coupling to the input voltage signal using the alternating current coupling circuit.
12. The method of claim 10 ,
wherein the input voltage regulating circuit includes a filtering circuit, and the modifying includes filtering the input voltage signal using the filtering circuit.
13. The system of claim 1 , wherein the input voltage signal is received from a common collector pin.
14. The system of claim 1 , wherein the regulated voltage signal includes a first modified pulse and a second modified pulse, the first modified pulse having a first edge and a second edge, wherein a magnitude of the first edge is different than a magnitude of the second edge.
15. The system of claim 5 , wherein the regulated voltage signal includes a first modified pulse and a second modified pulse, the first modified pulse having a first edge and a second edge, wherein a magnitude of the first edge is different than a magnitude of the second edge.
16. The method of claim 10 , wherein the regulated voltage signal includes a first modified pulse and a second modified pulse, the first modified pulse having a first edge and a second edge, wherein a magnitude of the first edge is different than a magnitude of the second edge.