IP Library Granted Patent US 9,787,320
Granted Patent B1
US 9,787,320 · App. 15/454,381 · Granted Oct 10, 2017

Methods and apparatus for an analog-to-digital converter

Inventor: Akinobu Onishi (Ota, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H03M3/464H03M1/12H03M1/1245H03M3/422
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Quick Facts
Patent No.
US 9,787,320
App. No.
15/454,381
Granted
Oct 10, 2017
Kind
B1
Abstract

Various embodiments of the present technology may comprise a method and apparatus for an analog-to digital converter (ADC). Methods and apparatus for an ADC according to various aspects of the present invention may operate in conjunction with a reference voltage that varies according to the frequency of a timing signal. By varying the reference voltage according to the frequency of the timing signal, the ADC generates a digital output having a substantially fixed voltage regardless of the frequency of the timing signal.

Claims (48)

1. An integrated circuit capable of receiving an input signal with a first voltage range, comprising:

a phase generator configured to generate a timing signal;

a reference voltage generator responsive to the phase generator and configured to generate a reference voltage comprising a magnitude that is inversely proportional to a frequency of the timing signal; and

an analog-to-digital converter with an adjustable full scale voltage, coupled to the reference voltage generator and responsive to the reference voltage;

wherein:

the adjustable full scale voltage is adjusted to substantially match the first voltage range; and

the analog-to-digital converter transmits a digital value with a substantially constant voltage.

2. The integrated circuit of claim 1 , further comprising a resistive element and a capacitive element coupled in series and coupled to an input terminal of the analog-to digital converter.

3. The integrated circuit of claim 1 , wherein the analog-to-digital converter comprises a digital-to-analog converter coupled to an output terminal of the analog-to-digital converter and the reference voltage generator, wherein the digital-to-analog converter receives the reference voltage.

4. The integrated circuit of claim 1 , wherein the analog-to-digital converter comprises a delta-sigma modulator having a fully differential topology.

5. The integrated circuit of claim 1 , wherein the analog-to-digital converter further comprises a digital circuit coupled to an output terminal of the delta-sigma modulator, comprising a decimation filter and a high-pass filter.

6. The integrated circuit of claim 1 , wherein the reference voltage generator comprises a primary circuit and a secondary circuit, wherein:

the primary circuit generates a first current and the reference voltage;

the secondary circuit generates a second current based on the frequency of the timing signal; and

the first current is responsive to the second current.

7. The integrated circuit of claim 1 , wherein the secondary circuit comprises a switched-capacitor resistor comprising a switching device and a capacitor.

8. The integrated circuit of claim 7 , wherein the secondary circuit comprises a low-pass filter coupled to the switched-capacitor resistor and a current mirror.

9. A method for signal conversion utilizing an analog-to-digital converter, comprising:

generating a timing signal with a frequency;

generating a reference voltage according to the frequency of the timing signal, wherein the reference voltage is inversely proportional to the frequency of the timing signal;

operating the analog-to-digital converter according to the reference voltage;

outputting, at an output of the analog-to-digital converter, a digital output with a substantially constant value.

10. The method of claim 9 , wherein operating the analog-to-digital converter according to the reference voltage results in matching a full scale voltage of the analog-to-digital converter with a voltage range of an input signal.

11. The method of claim 9 , wherein operating the analog-to-digital converter comprises utilizing a digital-to-analog converter to receive the reference voltage and charging a capacitor to a voltage potential.

12. The method of claim 9 , wherein operating the analog-to-digital converter comprises adjusting a full scale voltage of the analog-to-digital converter based on the reference voltage.

13. The method of claim 9 , wherein generating the reference voltage comprises generating a variable reference current based on the frequency of the timing signal.

14. A system, comprising:

a micro electro-mechanical device;

a circuit coupled to the micro electro-mechanical device, comprising:

a phase generator configured to generate a timing signal;

a reference voltage generator, coupled to the phase generator, configured to generate a reference voltage that is inversely proportional to the frequency of the timing signal;

an analog-to-digital converter coupled to the reference voltage generator, and configured to:

receive an input signal, with a first voltage range, from the micro electro-mechanical device;

operate according to the reference voltage;

output a digital value that is substantially fixed regardless of the frequency of the timing signal;

wherein a full scale voltage range of the analog-to-digital converter is adjusted according to the reference voltage.

15. The system of claim 14 , wherein the micro electro-mechanical device comprises a microphone.

16. The system of claim 14 , wherein the circuit further comprises:

a low-pass filter coupled between an output signal of micro electro-mechanical device and an input of the analog-to-digital converter.

17. The system of claim 16 , wherein the analog-to-digital converter comprises a delta-sigma modulator coupled to an output terminal of the low pass filter, wherein:

the delta-sigma modulator is configured to receive the input signal with the first voltage range; and

the delta-sigma modulator comprises a fully differential topology.

18. The system of claim 17 , wherein the analog-to-digital converter further comprises: a digital circuit coupled to an output terminal of the delta-sigma modulator, comprising a decimation filter and a high-pass filter.

19. The system of claim 14 , wherein the reference voltage generator comprises a primary circuit and a secondary circuit, wherein the secondary circuit generates a current based on the frequency of the timing signal, and the reference voltage generator is configured to generate a reference voltage according to the current of the secondary circuit.

20. The system of claim 19 , wherein the secondary circuit comprises:

a current mirror;

a switched-capacitor resistor; and

a low-pass filter.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 04481, FRAME 0541 Recorded Jun 22, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064072/0459 →
PATENT SECURITY AGREEMENT Recorded Nov 17, 2017
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 044481/0541 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 9, 2017
From: ONISHI, AKINOBU
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 041529/0079 →
Continuity (1)
Continuation 15276943 · Sep 27, 2016