According to one embodiment, A level shifter includes a first circuit configured to generate a first signal, the first signal being inverted and delayed signal of a second signal, a NAND circuit including a first input terminal and a second input terminal, the second signal being input to the first terminal, the first signal being input to the second terminal, a first transistor, a first voltage being applied to a first terminal of the first transistor, a second terminal of the first transistor being connected to a third input terminal of the NAND circuit, a third signal which inverts the second signal being applied to a gate of the first transistor, a second transistor, a second voltage being applied to a first terminal of the second transistor, the second voltage being higher than the first signal, a gate of the second transistor being connected to an output terminal, a third transistor, the second voltage being applied to a first terminal of the third transistor, a second terminal of the third transistor being connected to a second terminal of the second transistor, the second signal being applied to a gate of the third transistor, and a fourth transistor, a first terminal of the fourth transistor being connected to the second terminal of the third transistor, a second terminal of the fourth transistor being connected to the output terminal, an output terminal of the NAND circuit being connected to a gate of the fourth transistor.
1. A flash memory driver circuit configured to supply voltages to a row decoder for writing and reading data, comprising:
a control circuit configured to output a first signal having a first logic level at a first time and a second logic level, inverse of the first logic level, at a second time after the first time;
a logic level shifter circuit connected to receive the first signal as an input and output a second signal to an output terminal responsive to the first signal; and
a voltage driver circuit configured to controllably output a first voltage during a first operation and a second voltage during a second operation according to the second signal,
wherein the logic level shifter circuit is configured to:
output the second signal at a third voltage at the first time,
output the second signal at a fourth voltage higher than the third voltage and lower than a fifth voltage between the second time and a third time, and
output the second signal at the fifth voltage after the third time according to a predetermined delay after the second time.
2. The flash memory driver circuit, according to claim 1 , wherein the level shifter circuit further comprises:
a first circuit configured to generate a first signal, the first signal being inverted and delayed signal of a second signal;
a NAND circuit including a first input terminal and a second input terminal, the second signal being input to the first terminal, the first signal being input to the second terminal;
a first transistor, a first voltage being applied to a first terminal of the first transistor, a second terminal of the first transistor being connected to a third input terminal of the NAND circuit, a third signal which inverts the second signal being applied to a gate of the first transistor;
a second transistor, a second voltage being applied to a first terminal of the second transistor, the second voltage being higher than the first signal, a gate of the second transistor being connected to the output terminal;
a third transistor, the second voltage being applied to a first terminal of the third transistor, a second terminal of the third transistor being connected to a second terminal of the second transistor, the second signal being applied to a gate of the third transistor; and
a fourth transistor, a first terminal of the fourth transistor being connected to the second terminal of the third transistor, a second terminal of the fourth transistor being connected to the output terminal, an output terminal of the NAND circuit being connected to a gate of the fourth transistor.
3. The flash memory driver circuit according to claim 2 , wherein the first to third transistors are n channel depleted type MOS transistors, and the fourth transistor is p channel enhancement type MOS transistors.
4. The flash memory driver circuit according to claim 2 , further comprising:
a second circuit configured to output the first and third signal accordingly based on a fourth signal and a fifth signal, the fourth signal being input from outside, the fifth signal being inverted signal of the fourth signal.
5. The flash memory driver circuit according to claim 3 , further comprising:
a second circuit configured to output the first and third signal accordingly based on a fourth signal and a fifth signal, the fourth signal being input from outside, the fifth signal being inverted signal of the fourth signal.
6. The flash memory driver circuit according to claim 2 , further comprising:
fifth to seventh transistors, a first terminal of the fifth transistor being connected to the output terminal, a gate of the fifth transistor being connected to a ground voltage, a first terminal of the sixth transistor being connected to a second terminal of the fifth transistor, a second terminal of the sixth transistor being connected to a first terminal of the seventh transistor, the first voltage being applied to a gate of the sixth transistor, a second terminal of the seventh transistor being connected to the ground voltage.
7. The flash memory driver circuit according to claim 3 , further comprising:
fifth to seventh transistors, a first terminal of the fifth transistor being connected to the output terminal, a gate of the fifth transistor being connected to a ground voltage, a first terminal of the sixth transistor being connected to a second terminal of the fifth transistor, a second terminal of the sixth transistor being connected to a first terminal of the seventh transistor, the first voltage being applied to a gate of the sixth transistor, a second terminal of the seventh transistor being connected to the ground voltage.
8. The flash memory driver circuit according to claim 5 , further comprising:
fifth to seventh transistors, a first terminal of the fifth transistor being connected to the output terminal, a gate of the fifth transistor being connected to a ground voltage, a first terminal of the sixth transistor being connected to a second terminal of the fifth transistor, a second terminal of the sixth transistor being connected to a first terminal of the seventh transistor, the first voltage being applied to a gate of the sixth transistor, a second terminal of the seventh transistor being connected to the ground voltage.
9. The flash memory driver circuit according to claim 7 , wherein the fifth transistor is n channel depleted type MOS transistor, and the sixth and seventh transistors are n channel enhancement type MOS transistors.
10. The flash memory driver circuit according to claim 8 , wherein the fifth transistor is n channel depleted type MOS transistor, and the sixth and seventh transistors are n channel enhancement type MOS transistors.
11. The flash memory driver circuit according to claim 9 , further comprising:
an eighth transistor, a first terminal of the eighth transistor being connected to the second terminal of the sixth transistor, the third voltage being applied to a second terminal of the eighth transistor, the first voltage being applied to a gate of the eighth transistor.
12. The flash memory driver circuit according to claim 10 , further comprising:
an eighth transistor, a first terminal of the eighth transistor being connected to the second terminal of the sixth transistor, the third voltage being applied to a second terminal of the eighth transistor, the first voltage being applied to a gate of the eighth transistor.