IP Library Granted Patent US 10,331,584
Granted Patent B2
US 10,331,584 · App. 15/454,974 · Granted Jun 25, 2019

Internal system namespace exposed through use of two local processors and controller memory buffer with two reserved areas

Inventor: Julien Margetts (Thame, GB)
Assignee: Toshiba Memory Corporation
G06F13/1668G06F3/0604G06F3/0616G06F3/0658G06F3/0659G06F3/0679G06F12/0246G06F2212/1056G06F2212/7205
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Quick Facts
Patent No.
US 10,331,584
App. No.
15/454,974
Granted
Jun 25, 2019
Kind
B2
Abstract

A solid state drive (SSD) and a method for managing data stored in the SSD is disclosed. In one embodiment, the SSD includes a memory controller and a controller memory buffer within the memory controller. The SSD further includes a host interface communicatively coupled to the memory controller and configured to receive a set of host commands from a host device. A first local processor of the SSD is configured to generate a set of local commands, and a second local processor of the SSD is configured to execute the set of local commands and the set of host commands. The memory controller is configured to store the set of local commands in a first area of the controller memory buffer reserved for the first local processor and to store the set of host commands in a second area of the controller memory buffer reserved for the host device.

Claims (44)

1. A method of managing data stored in a solid state drive (SSD), the method comprising:

reserving a first area and a second area of a controller memory buffer within a memory controller;

generating, by a first local processor, a set of local commands according to a storage protocol standard;

receiving, by a host interface communicatively coupled to the memory controller, a set of host commands from a host device according to the storage protocol standard;

storing the set of local commands in the first area; and the set of host commands in the second area; and

executing, by a second local processor, the set of local commands and the set of host commands according to the a storage protocol standard.

2. The method of claim 1 , further comprising:

generating, by the first local processor, local system data; and

storing the local system data in the first area.

3. The method of claim 2 , further comprising:

writing, by the second local processor, local system data in the first area to one or more of non-volatile memory devices communicatively coupled to the memory controller when the set of local commands includes a write command.

4. The method of claim 2 , further comprising:

writing, by the second local processor, local system data in one or more of the non-volatile memory devices communicatively coupled to the memory controller to the first area when the set of local commands includes a read command.

5. The method of claim 2 , wherein the local system data includes metadata of host data written to one or more non-volatile memory devices communicatively coupled to the memory controller, logical-to-physical look up tables, read or write counts of logical block addresses, or timestamps of logical block address updates.

6. The method of claim 1 , further comprising:

receiving, by the host interface, host data from the host device; and

storing the host data in the second area.

7. The method of claim 6 , further comprising:

writing, by the second local processor, host data in the second area to one or more non-volatile memory devices communicatively coupled to the memory controller when the set of host commands includes a write command.

8. The method of claim 6 , further comprising:

retrieving, by the second local processor, host data in one or more non-volatile memory devices communicatively coupled to the memory controller when the set of host commands includes a read command.

9. The method of claim 1 , further comprising:

storing, by the second local processor, a completion message in the first area after one of the set of local commands has been executed.

10. The method of claim 1 , wherein the first local processor is a flash translation layer (FTL) processor or a flash interface layer (FIL) processor, and the second local processor is a command layer processor.

11. The method of claim 1 , wherein the first local processor generates a set of local commands independent from the set of host commands.

12. The method of claim 1 , wherein the storage protocol standard is NVMe.

13. A solid state drive (SSD) comprising:

a memory controller;

a controller memory buffer within the memory controller;

a first local processor configured to generate a set of local commands according to a storage protocol standard;

a host interface communicatively coupled to the memory controller and configured to receive a set of host commands from a host device according to the storage protocol standard;

a second local processor configured to execute the set of local commands and the set of host commands according to the storage protocol standard,

wherein the memory controller is configured to store the set of local commands in a first area of the controller memory buffer reserved for the first local processor and to store the set of host commands in a second area of the controller memory buffer reserved for the host device.

14. The SSD of claim 13 , wherein the memory controller is further configured to store local system data generated by the first local processor in the first area.

15. The SSD of claim 14 , wherein the set of local commands includes a write command, and the second local processor is further configured to write local system data stored in the first area to one or more non-volatile memory devices communicatively coupled to the memory controller.

16. The SSD of claim 14 , wherein the set of local commands includes a read command, and the second local processor is further configured to write local system data stored in one or more non-volatile memory devices communicatively coupled to the memory controller to the first area.

17. The SSD of claim 14 , wherein the local system data includes metadata of host data written to one or more non-volatile memory devices communicatively coupled to the memory controller, logical-to-physical look up tables, read or write counts of logical block addresses, or timestamps of logical block address updates.

18. The SSD of claim 13 , wherein the host interface is further configured to receive host data from the host device, and the memory controller is further configured to store the host data in the second area.

19. The SSD of claim 18 , wherein the set of host commands includes a write command, and the second local processor is further configured to write host data stored in the second area to one or more non-volatile memory devices communicatively coupled to the memory controller.

20. The SSD of claim 18 , wherein the set of host commands includes a read command, and the second local processor is further configured to retrieve host data stored in one or more non-volatile memory devices communicatively coupled to the memory controller.

21. The SSD of claim 13 , wherein the second local processor is configured to store a completion message in the first area after one of the set of local commands has been executed.

22. The SSD of claim 13 , wherein the first local processor is a flash translation layer (FTL) processor or a flash interface layer (FIL) processor, and the second local processor is a command layer processor.

23. The SSD of claim 13 , wherein the first local processor generates a set of local commands independent from the set of host commands.

24. The SSD of claim 13 , wherein the storage protocol standard is NVMe.

Assignments (8)
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2018
From: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 046870/0038 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2018
From: MARGETTS, JULIEN
To: OCZ STORAGE SOLUTIONS LIMITED
Reel/Frame 046365/0324 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2018
From: MARGETTS, JULIEN
To: OCZ STORAGE SOLUTIONS LIMITED
Reel/Frame 046365/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 15, 2018
From: OCZ STORAGE SOLUTIONS LIMITED
To: TOSHIBA AMERICA ELECTRONIC COMPONENTS, INC.
Reel/Frame 046365/0391 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 1, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043397/0380 →
Continuity (1)
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