Semiconductor memory device

1. A semiconductor memory device, comprising:

a substrate having a surface;

a first interconnect facing the surface of the substrate in a first direction;

a second interconnect, the first interconnect being provided between the second interconnect and the substrate in the first direction;

a plurality of third interconnects extending in a second direction, being arranged to be separated from each other along the first direction, the second interconnect being provided between the third interconnects and the first interconnect in the first direction, the second direction crossing the first direction;

a fourth interconnect extending in a third direction crossing the first direction, the third interconnects being provided between the fourth interconnect and the second interconnect in the first direction;

a first semiconductor member extending in the first direction and piercing the third interconnects, the first semiconductor member being connected between the fourth interconnect and the second interconnect;

a first charge storage member provided between the first semiconductor member and at least one of the third interconnects;

a fifth interconnect extending in the third direction, the third interconnects being provided between the fifth interconnect and the second interconnect in the first direction;

a second semiconductor member extending in the first direction and piercing the third interconnects, the second semiconductor member being connected between the fifth interconnect and the second interconnect

a second charge storage member provided between the second semiconductor member and at least one of the third interconnects;

a sixth interconnect, the third interconnects being provided between the sixth interconnect and the second interconnect in the first direction; and

a conductive member extending in the first direction and piercing the third interconnects and the second interconnect while being insulated therefrom, the conductive member being connected between the sixth interconnect and the first interconnect.

2. The device according to claim 1 , further comprising seventh and eighth interconnects extending in the second direction, being provided between the fourth interconnect and the third interconnects in the first direction and between the fifth interconnect and the third interconnects in the first direction, and being separated from each other in the third direction,

the conductive member being disposed between the seventh and eighth interconnects.

3. The device according to claim 1 , wherein

a transistor is formed in the surface of the substrate, and

the first interconnect is connected to a source, a drain, or a gate of the transistor.

4. The device according to claim 1 , wherein

each of the fourth and fifth interconnects functions as a bit line, and

a position of the sixth interconnect in the first direction is substantially the same with positions of the fourth and fifth interconnects in the first direction.

5. The device according to claim 1 , wherein

the conductive member pierces the third interconnects to define holes in the third interconnects, respectively, and

when viewed in the first direction, a shape of an outer circumference of the conductive member corresponding to shapes of inner circumferences of the holes.

6. The device according to claim 1 , wherein

at least part of the conductive member between an upper most one of the third interconnects and the first interconnect in the first direction is formed as one body.

7. The device according to claim 2 , further comprising first and second insulating members extending in the second direction, being provided between the seventh and eighth interconnects in the third direction, and being separated from each other in the second direction,

the conductive member being disposed between the first and second insulating members in the second direction.

8. The device according to claim 3 , wherein

a memory cell is formed in plurality between each of the first and second semiconductor members and each of the third interconnects, and

the first interconnect and the transistor form a control circuit configured to control the memory cells.

9. The device according to claim 4 , further comprising

a third semiconductor member extending in the first direction and piercing the third interconnects, the third semiconductor member being disposed between the first semiconductor member and the second semiconductor member in the second direction and being not connected with a bit line.

10. A semiconductor memory device, comprising:

a substrate having a surface;

a first interconnect facing the surface of the substrate in a first direction;

a second interconnect facing the surface of the substrate in the first direction;

a third interconnect, the first interconnect and the second interconnect being provided between the third interconnect and the substrate in the first direction;

a plurality of fourth interconnects extending in a second direction, and being arranged to be separated from each other along the first direction, the third interconnect being provided between the fourth interconnects and the first interconnect in the first direction and between the fourth interconnects and the second interconnect in the first direction, the second direction crossing the first direction;

a fifth interconnect extending in a third direction crossing the first direction, the fourth interconnects being provided between the fifth interconnect and the third interconnect in the first direction;

a semiconductor member extending in the first direction and piercing the fourth interconnects, the semiconductor member being connected between the fifth interconnect and the third interconnect;

a charge storage member provided between the semiconductor member and at least one of the fourth interconnects;

a sixth interconnect, the fourth interconnects being provided between the sixth interconnect and the third interconnect in the first direction;

a first conductive member extending in the first direction and piercing the fourth interconnects and the third interconnect while being insulated therefrom, the first conductive member being connected between the sixth interconnect and the first interconnect;

a seventh interconnect, the fourth interconnects being provided between the seventh interconnect and the third interconnect in the first direction;

a second conductive member extending in the first direction and piercing the fourth interconnects and the third interconnect while being insulated therefrom, the second conductive member being connected between the seventh interconnect and the second interconnect,

the semiconductor member being provided between the first conductive member and the second conductive member in the second direction.

11. The device according to claim 10 , wherein first and second transistors are formed in the surface of the substrate, and

the first and second interconnects are connected to sources, drains, or gates of the first and second transistors, respectively.

12. The device according to claim 10 ,

the fifth interconnect functions as a bit line, and

a position of the first interconnect in the first direction is substantially the same with positions of the sixth and seventh interconnects in the first direction.

13. The device according to claim 10 , wherein

the first conductive member pierces the fourth interconnects to define first holes in the fourth interconnects, respectively,

the second conductive member pierces the fourth interconnects to define second holes in the fourth interconnects, respectively, and

when viewed in the first direction, a shape of an outer circumference of the first conductive member corresponding to shapes of inner circumferences of the first holes, and a shape of an outer circumference of the second conductive member corresponding to shapes of inner circumferences of the second holes.

14. The device according to claim 10 , further comprising eighth and ninth interconnects extending in the second direction, being provided between the fifth interconnect and the fourth interconnects in the first direction, and being separated from each other in the third direction, and the first and second conductive members being disposed between the eighth and ninth interconnects in the third direction.

15. The device according to claim 10 , wherein

at least part of the first conductive member between an uppermost one of the fourth interconnects and the first interconnect in the first direction is formed as one body, and

at least part of the second conductive member between the uppermost one of the fourth interconnects and the second interconnect in the first direction is formed as one body.

16. The device according to claim 14 , further comprising

a first insulating member extending in the second direction, being provided between the eighth and ninth interconnects in the third direction,

the first insulating member being disposed between the first and second conductive members.