Refresh time detection circuit and semiconductor device including the same
A refresh time detection circuit and a semiconductor device including the same may be provided. The refresh time detection circuit may include a code generator configured to generate a code signal for detecting a refresh time. The refresh time detection circuit may include a latch circuit configured to generate a latch signal by latching the code signal according to a fail signal, and generate a pre-code signal and a post-code signal by latching each latch signal according to a pre-enable signal and a post-enable signal. The refresh time detection circuit may include a subtractor configured to output a refresh detection signal by performing subtraction between the pre-code signal and the post-code signal. The refresh time detection circuit may include a comparator configured to generate a detection signal by comparing the refresh detection signal with an offset signal based on the post-enable signal.
1. A refresh time detection circuit comprising:
a code generator configured to generate a code signal for detecting a refresh time;
a latch circuit configured to generate a latch signal by latching the code signal according to a fail signal, and generate a pre-code signal and a post-code signal by latching each latch signal according to a pre-enable signal and a post-enable signal;
a subtractor configured to output a refresh detection signal by performing subtraction between the pre-code signal and the post-code signal; and
a comparator configured to generate a detection signal by comparing the refresh detection signal with an offset signal based on activation of the post-enable signal.
2. The refresh time detection circuit according to claim 1 , wherein the code generator is configured to sequentially generate a plurality of code signals,
wherein the code generator is configured to sequentially increase a value of the code signal based on a command signal.
3. The refresh time detection circuit according to claim 1 , wherein the latch circuit includes:
a first latch configured to latch the code signal by synchronizing with the fail signal, and generate the latch signal;
a second latch configured to output the pre-code signal by latching the latch signal based on the pre-enable signal; and
a third latch configured to generate the post-code signal by latching the latch signal based on the post-enable signal.
4. The refresh time detection circuit according to claim 1 , wherein:
if a value of the refresh detection signal is greater than a value of the offset signal during an activation period of the post-enable signal, the comparator is configured to output the detection signal at a first logic level; and
if a value of the refresh detection signal is less than a value of the offset signal during the activation period of the post-enable signal, the comparator is configured to output the detection signal at a second logic level.
5. The refresh time detection circuit according to claim 1 , wherein the fail signal includes specific information in which refresh data is maintained or lost when the refresh time is changed.
6. The refresh time detection circuit according to claim 1 , wherein the pre-enable signal is activated during a temperature stress application time period.
7. The refresh time detection circuit according to claim 1 , wherein the post-enable signal is generated by synchronizing with the fail signal.
8. The refresh time detection circuit according to claim 7 , wherein the post-enable signal is activated after lapse of the temperature stress application time period.
9. The refresh time detection circuit according to claim 7 , wherein the post-enable signal is generated by synchronizing with a second activation period of the fail signal after a first activation period of the fail signal.
10. A semiconductor device comprising:
a first input buffer configured to buffer a command signal received from an external test device;
a refresh time detection circuit configured to latch a code signal corresponding to an output signal of the first input buffer according to a fail signal, a pre-enable signal, and a post-enable signal, generate a pre-code signal and a post-code signal activated at different times, and output a detection signal by comparing a refresh detection signal obtained by subtraction between the pre-code signal and the post-code signal with an offset signal; and
an output buffer configured to buffer the detection signal, and output the buffered detection signal to the external test device.
11. The semiconductor device according to claim 10 , wherein the refresh time detection circuit includes:
a code generator configured to generate the code signal for detecting a refresh time;
a latch circuit configured to generate a latch signal by latching the code signal according to the fail signal, and generate the pre-code signal and the post-code signal by latching each latch signal according to the pre-enable signal and the post-enable signal;
a subtractor configured to output the refresh detection signal by performing subtraction between the pre-code signal and the post-code signal; and
a comparator configured to generate the detection signal by comparing the refresh detection signal with the offset signal based on activation of the post-enable signal.
12. The semiconductor device according to claim 11 , wherein the code generator is configured to sequentially generate a plurality of code signals,
wherein the code generator is configured to sequentially increase a value of the code signal based on the command signal.
13. The semiconductor device according to claim 11 , wherein the latch circuit includes:
a first latch configured to latch the code signal by synchronizing with the fail signal, and generate the latch signal;
a second latch configured to output the pre-code signal by latching the latch signal based on the pre-enable signal; and
a third latch configured to generate the post-code signal by latching the latch signal based on the post-enable signal.
14. The semiconductor device according to claim 11 , wherein:
if a value of the refresh detection signal is greater than a value of the offset signal during an activation period of the post-enable signal, the comparator is configured to output the detection signal at a first logic level; and
if a value of the refresh detection signal is less than a value of the offset signal during the activation period of the post-enable signal, the comparator is configured to output the detection signal at a second logic level.
15. The semiconductor device according to claim 11 , wherein the fail signal includes specific information in which refresh data is maintained or lost when the refresh time is changed.
16. The semiconductor device according to claim 11 , wherein the pre-enable signal is activated during a temperature stress applying time period.
17. The semiconductor device according to claim 11 , wherein the post-enable signal is generated by synchronizing with the fail signal.
18. The semiconductor device according to claim 17 , wherein the post-enable signal is activated after lapse of the temperature stress applying time period.
19. The semiconductor device according to claim 10 , further comprising:
a second input buffer configured to buffer the fail signal, and output the buffered fail signal to the refresh time detection circuit.
20. The semiconductor device according to claim 10 , wherein the refresh time detection circuit is coupled to a plurality of banks to detect a refresh time for each bank.