Calibration of high speed ananlog-to-digital converters

1. A system comprising:

a signal generator for providing a first signal during a calibration mode for the system;

parallel analog-to-digital converters (ADCs) for providing ADC outputs associated with the first signal;

first parallel filters for providing derivative signals associated with the ADC outputs;

second parallel filters for providing first band-stop filtered signals associated with the ADC outputs;

third parallel filters for providing second band-stop filtered signals associated with the derivative signals;

a first multiplier circuit for multiplying the first and the second band-stop filtered signals to provide first multiplied signals including correlation information from the first and the second band-stop filtered signals;

an adaptive gain circuit for selecting a portion of the first multiplied signals; and

an accumulator circuit for (a) providing accumulator output for the selection of the portion of the first multiplied signals and (b) storing the accumulator output into a memory circuit.

2. The system of claim 1 , wherein the system further comprises:

the adaptive gain circuit for the selecting selects the portion in accordance with a predetermined convergence speed and a predetermined system error.

3. The system of claim 2 , wherein the accumulator output is an estimated time offset for calibrating the system.

4. The system of claim 3 , further comprising, as part of a correction mode:

a second multiplier circuit for multiplying the estimated time offset and the first band-stop filtered signals to provide a second multiplied signal; and

a subtraction circuit for providing subtracted signals from subtracting the second multiplied signal and the ADC outputs.

5. The system of claim 1 , wherein the adaptive gain circuit is configured for applying a gain as a fixed or a variable gain during the selecting.

6. The system of claim 4 , wherein the system further comprising the correction mode is separable from the system and in communication with the system.

7. The system of claim 1 , wherein the system further comprising the memory circuit for the storing of the accumulator output is a calibrated system.

8. The system of claim 1 , wherein the accumulator circuit is configured for signal integration, over time, for the selection of the portion of the first multiplied signals to provide estimated time offset, wherein the estimated time offsets applied to the ADC outputs reflect a calibration of the system.

9. The system of claim 8 , wherein the accumulator circuit provides the estimated time offset using a least mean square (LMS) calculation applied to the selection of the portion of the first multiplied signals.

10. The system of claim 1 , wherein the first parallel filters provide the derivative signals using a Hilbert transform.

11. A method comprising:

providing, from a signal generator, a first signal during a calibration mode;

providing, using parallel analog-to-digital converters (ADCs), ADC outputs associated with the first signal;

providing, using first parallel filters, derivative signals associated with the ADC outputs;

providing, using second parallel filters, first band-stop filtered signals associated with the ADC outputs;

providing, using third parallel filters, second band-stop filtered signals associated with the derivative signals;

multiplying, using a first multiplier circuit, the first and the second band-stop filtered signals to provide first multiplied signals including correlation information from the first and the second band-stop filtered signals;

selecting, using an adaptive gain circuit, a portion of the first multiplied signals; and

providing, from an accumulator circuit, accumulator output for the selection of the portion of the first multiplied signals, wherein the accumulator output is stored into a memory circuit.

12. The method of claim 11 , wherein the selecting is in accordance with a predetermined convergence speed and a predetermined system error.

13. The method of claim 12 , wherein the accumulator output is an estimated time offset for calibrating the system.

14. The method of claim 13 , wherein the method further comprises a correction mode for:

multiplying, using a second multiplier circuit, the estimated time offset and the first band-stop filtered signals to provide a second multiplied signal; and

providing, using a subtraction circuit, subtracted signals from subtracting the second multiplied signal and the ADC outputs.

15. The method of claim 11 , wherein the selecting for the portion of the first multiplied signals further comprises applying a gain as a fixed or a variable gain to the portion of the first multiplied signals.

16. The method of claim 14 , wherein further comprising: providing separable components for performing the correction mode and the calibration mode.

17. The method of claim 11 , wherein the method further comprises:

storing, using the memory circuit, the accumulator output, thereby representing available calibration for a system implementing the method.

18. The method of claim 11 , wherein the method further comprises:

signal integration, over time, for the selection of the portion of the first multiplied signals to provide estimated time offset, wherein the estimated time offsets applied to the ADC outputs reflect a calibration of the system.

19. The method of claim 18 , wherein the providing of the estimated time offset uses a least mean square (LMS) calculation applied to the selection of the portion of the first multiplied signals.

20. The method of claim 1 , wherein the method further comprises:

providing, using the first parallel filters, the derivative signals by applying a Hilbert transform.