Memory device

1. A memory device comprising:

a memory cell array including memory cells;

a generation circuit generating a reference current;

a sense amplifier comparing a cell current flowing through a memory cell with the reference current and sensing data stored in the memory cell;

a first clamp transistor connected between a first input terminal of the sense amplifier and the memory cell;

a second clamp transistor connected between a second input terminal of the sense amplifier and the generation circuit;

a first interconnect layer connected to a gate of the first clamp transistor and extending in a first direction;

a second interconnect layer connected to a gate of the second clamp transistor, extending in the first direction, and arranged adjacent to the first interconnect layer; and

a first shield line arranged adjacent to one of the first interconnect layer and the second interconnect layer and extending in the first direction, a fixed voltage being applied to the first shield line,

wherein a first interval between the first interconnect layer and the second interconnect layer is narrower than a second interval between the one of the first interconnect layer and the second interconnect layer and the first shield layer.

2. The device of claim 1 , further comprising a second shield line arranged adjacent to the other of the first interconnect layer and the second interconnect layer and extending in the first direction, a fixed voltage being applied to the second shield line,

wherein the first interval is narrower than a third interval between the other of the first interconnect layer and the second interconnect layer and the second shield layer.

3. The device of claim 1 , further comprising:

sense amplifiers including the sense amplifier and provided to correspond to the memory cells;

first clamp transistors including the first clamp transistor and connected to the sense amplifiers; and

second clamp transistors including the second clamp transistor and connected to the sense amplifiers,

wherein the first interconnect layer is connected to gates of the first clamp transistors, and

the second interconnect layer is connected to gates of the second clamp transistors.

4. The device of claim 1 , further comprising an equalizing circuit connecting the first interconnect layer and the second interconnect layer in response to a control Signal.

5. The device of claim 4 , wherein

the equalizing circuit includes a MOS transistor connected between the first interconnect layer and the second interconnect layer, and

the control signal is supplied to a gate of the MOS transistor.

6. The device of claim 4 , further comprising sense amplifiers including the sense amplifier and provided to correspond to the memory cells,

wherein the sense amplifiers are divided into a first group and a second group, and

the equalizing circuit is arranged between the first group and the second group.

7. The device of claim 1 , further comprising a third interconnect layer connecting the first interconnect layer and the second interconnect layer.

8. The device of claim 1 , further comprising third interconnect layers connecting the first interconnect layer and the second interconnect layer.

9. The device of claim 7 , further comprising sense amplifiers including the sense amplifier and provided to correspond to the memory cells,

wherein the sense amplifiers are divided into a first group and a second group, and

the third interconnect layer is arranged between the first group and the second group.

10. The device of claim 1 , further comprising a bit line connecting the first clamp transistor and the memory cell.

11. The device of claim 1 , wherein the fixed voltage is one of a power supply voltage and a ground voltage.

12. The device of claim 1 , wherein

a voltage of the first interconnect layer is different from a voltage of the second interconnect layer in a first operating mode, and

the voltage of the first interconnect layer is equal to the voltage of the second interconnect layer in a second operating mode.

13. The device of claim 1 , wherein the memory cell includes a variable resistive element.

14. The device of claim 1 , wherein the memory cell includes a magnetoresistive element.

15. The device of claim 1 , wherein the memory device is a spin-transfer torque magnetoresistive random access memory (STT-MRAM).