Semiconductor storage device including a controller configured to execute a first write and a second write
According to one embodiment, a semiconductor storage device includes a first memory cell capable of storing n-bit data (n is a natural number not less than 4). When receiving first data, including first and second bits of the n-bit data, from a controller, the semiconductor storage device writes the received first data to the first memory cell. After receiving the first data, when the semiconductor storage device receives second data including third and fourth bits of the n-bit data, the semiconductor storage device reads the first and second bits from the first memory cell and writes the n-bit data to the first memory cell based on the read first and second bits and the received second data.
1. A semiconductor storage device comprising:
first and second memory cells;
a third memory cell, one end of the third memory cell being connected to one end of the first memory cell;
a fourth memory cell, one end of the fourth memory cell being connected to one end of the second memory cell;
a first select transistor connected to another end of the third memory cell;
a second select transistor connected to another end of the fourth memory cell;
a first word line connected to each gate of the first and second memory cells;
a second word line connected to each gate of the first and second memory cells, the second word line being adjacent to the first word line; and
a controller configured to execute a first write and a second write, wherein
in a write operation, the controller sequentially executes the first write for the third memory cell, the second write for the first memory cell, and the first write for the fourth memory cell.
2. The device of claim 1 , wherein
in the first write, a first program pulse is applied a plurality of times to a selected word line, wherein a voltage of the first program pulse increases, from a first voltage, by a second voltage for each application of the first program pulse,
in the second write, a second program pulse is applied a plurality of times to a selected word line, wherein a voltage of the second program pulse increases, from a third voltage, by a fourth voltage for each application of the second program pulse,
the first voltage is higher than the third voltage, and
the second voltage is higher than the fourth voltage.
3. The device of claim 1 , wherein, in the write operation, the controller executes the second write for the second memory cell after the first write for the fourth memory cell.
4. The device of claim 1 , further comprising:
fifth and sixth memory cells, the first word line being connected to each gate of the fifth and sixth memory cells;
a seventh memory cell, a gate of the seventh memory cell being connected to the first word line, one end of the seventh memory cell being connected to one end of the fifth memory cell;
an eighth memory cell, a gate of the eighth memory cell being connected to the second word line, one end of the eighth memory cell being connected to one end of the sixth memory cell;
a third select transistor connected to another end of the seventh memory cell; and
a fourth select transistor connected to another end of the eighth memory cell, wherein
in the write operation, the controller executes the first write for the third memory cell after sequentially executing the first write for the first memory cell, the first write for the second memory cell, the first write for the fifth memory cell, and the first write for the sixth memory cell.
5. The device of claim 4 , wherein
in the first write, a first program pulse is applied a plurality of times to a selected word line, wherein a voltage of the first program pulse increases, from a first voltage, by a second voltage for each application of the first program pulse,
in the second write, a second program pulse is applied a plurality of times to a selected word line, wherein a voltage of the second program pulse increases, from a third voltage, by a fourth voltage for each application of the second program pulse,
the first voltage is higher than the third voltage, and
the second voltage is higher than the fourth voltage.
6. The device of claim 4 , further comprising:
a ninth memory cell connected between the other end of the third memory cell and the first select transistor;
a tenth memory cell connected between the other end of the fourth memory cell and the second select transistor;
an eleventh memory cell connected between the other end of the seventh memory cell and the third select transistor;
a twelfth memory cell connected between the other end of the eighth memory cell and the fourth select transistor; and
a third word line connected to each gate of the ninth to twelfth memory cells, the third word line being adjacent to the second word line, wherein
in the write operation, the controller executes the first write for the ninth memory cell after the second write for the sixth memory cell.
7. The device of claim 1 , wherein
in the write operation, the controller executes the first write for the third memory cell when the controller receives a first command set from a host apparatus, and executes the second write for the first memory cell when the controller receives a second command set from the host apparatus,
the first command set includes first data and a first command instructing the controller to execute the first write, and
the second command set includes second data and a second command instructing the controller to execute the second write.
8. The device of claim 7 , wherein
in the write operation, the controller executes the first write for the first memory cell when the controller receives a third command set from the host apparatus before the controller receives the first command set, and
the third command set includes the first command and the second data.
9. A semiconductor storage device comprising:
first to fourth memory cells;
a fifth memory cell, one end of the fifth memory cell being connected to one end of the first memory cell;
a sixth memory cell, one end of the sixth memory cell being connected to one end of the second memory cell;
a seventh memory cell, one end of the seventh memory cell being connected to one end of the third memory cell;
a eighth memory cell, one end of the eighth memory cell being connected to one end of the fourth memory cell;
a first select transistor connected to another end of the fifth memory cell;
a second select transistor connected to another end of the sixth memory cell;
a third select transistor connected to another end of the seventh memory cell;
a fourth select transistor connected to another end of the eighth memory cell;
a first word line connected to each gate of the first to fourth memory cells;
a second word line connected to each gate of the fifth to eighth memory cells, the second word line being adjacent to the first word line; and
a controller configured to execute a first write and a second write, wherein
in a write operation, the controller sequentially executes the first write for the first memory cell, the first write for the second memory cell, the first write for the third memory cell, the first write for the fourth memory cell, the first write for the fifth memory cell, and the second write for the first memory cell.
10. The device of claim 9 , wherein
in the first write, a first program pulse is applied a plurality of times to a selected word line, wherein a voltage of the first program pulse increases, from a first voltage, by a second voltage for each application of the first program pulse,
in the second write, a second program pulse is applied a plurality of times to a selected word line, wherein a voltage of the second program pulse increases, from a third voltage, by a fourth voltage for each application of the second program pulse,
the first voltage is higher than the third voltage, and
the second voltage is higher than the fourth voltage.
11. The device of claim 9 , wherein, in the write operation, the controller executes the first write for the sixth memory cell after the second write for the first memory cell.
12. The device of claim 11 , wherein, in the write operation, the controller executes the second write for the second memory cell after the first write for the sixth memory cell.
13. The device of claim 9 , wherein
in the write operation, the controller executes the first write for the first memory cell when the controller receives a first command set from a host apparatus, and executes the second write for the first memory cell when the controller receives a second command set from the host apparatus,
the first command set includes first data and a first command instructing the controller to execute the first write, and
the second command set includes the first data and a second command instructing the controller to execute the second write.
14. The device of claim 9 , further comprising:
a ninth memory cell connected between the other end of the fifth memory cell and the first select transistor;
a tenth memory cell connected between the other end of the sixth memory cell and the second select transistor;
an eleventh memory cell connected between the other end of the seventh memory cell and the third select transistor;
a twelfth memory cell connected between the other end of the eighth memory cell and the fourth select transistor; and
a third word line connected to each gate of the ninth to twelfth memory cells, the third word line being adjacent to the second word line, wherein
in the write operation, the controller executes the first write for the ninth memory cell after the second write for the fourth memory cell.