IP Library Granted Patent US 10,341,020
Granted Patent B2
US 10,341,020 · App. 15/459,647 · Granted Jul 2, 2019

Flexible ethernet logical lane aggregation

Inventors: Rob Stone (Berkeley, CA); Eric Baden (Saratoga, CA)
Assignee: Avago Technologies International Sales Pte. Limited
H04B10/25H04L47/10
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Quick Facts
Patent No.
US 10,341,020
App. No.
15/459,647
Granted
Jul 2, 2019
Kind
B2
Abstract

A system or method for logical lane aggregation provides data across a first set of interconnect lanes and determines that at least one interconnect lane is unavailable. The system or method redistributes data to a second set of interconnect lanes, the second set not including the at least one interconnect lane, in response to the at least one interconnect lane being unavailable. The system or method can be used to provide flexible Ethernet logical lane aggregation (FELLA).

Claims (40)

1. A method for logical lane aggregation, the method comprising:

providing data across a first set of interconnect lanes;

in response to receiving a power reduction message to enable power saving, determining that at least one interconnect lane among the first set of interconnect lanes is to be made unavailable; and

redistributing data to a second set of interconnect lanes, the second set not including the at least one interconnect lane in response to the at least one interconnect lane being unavailable.

2. The method of claim 1 , further comprising:

adjusting alignment marker insertion logic to map alignment markers to the second set of interconnect lanes.

3. The method of claim 1 , wherein the interconnect lanes are Ethernet electrical lines or Ethernet optical lanes.

4. The method of claim 1 , wherein the redistributing data to the second set of interconnect lanes enables a power saving mode.

5. The method of claim 1 , wherein the redistributing data uses a symbol distribution unit in a physical coding sublayer to provide data to the second set in a round robin order.

6. The method of claim 1 , wherein the determining that at least one interconnect lane is unavailable is performed by a fault detector using an input from an optical module.

7. The method of claim 1 , wherein the determining that at least one interconnect lane is unavailable is performed by a fault detector receiving a power down command.

8. The method of claim 7 , further comprising:

determining that the at least one interconnect lane becomes available; and

redistributing data to the first set of interconnect lanes.

9. The method of claim 8 , further comprising:

adjusting alignment marker insertion logic to map the alignment markers to the first set of interconnect lanes.

10. A network device, comprising:

a media access sublayer; and

a physical coding sublayer configured to:

provide data across a first set of interconnect lanes;

in response to receiving a power reduction message to enable power saving, determine that at least one interconnect lane among the first set of interconnect lanes is to be made unavailable; and

redistribute data to a second set of interconnect lanes, the second set not including the at least one interconnect lane.

11. The network device of claim 10 , wherein the network device is an Ethernet device.

12. The network device of claim 10 , wherein the media access sublayer is paused while the physical coding sublayer is configured to redistribute data.

13. The network device of claim 10 , wherein the first set of interconnect lanes comprises either eight optical interconnect lanes or four optical interconnect lanes.

14. The network device of claim 10 , wherein the physical coding sublayer is configured to provide a message indicative of the second set of data interconnect lines to a receiving network device.

15. The network device of claim 10 , wherein the physical coding sublayer is configured to adjust alignment marker insertion logic to map alignment markers to the second set of interconnect lanes.

16. The network device of claim 10 , further comprising:

a physical medium attachment (PMA) sublayer comprising components associated with the first set of interconnect lanes, wherein at least one component associated with the at least one interconnect lane is disabled in response to the at least one interconnect lane being unavailable.

17. The network device of claim 10 , further comprising:

a physical medium dependent (PMD) sublayer comprising transmitters associated with the first set of interconnect lanes, wherein at least one transmitter associated with the at least one interconnect lane is disabled in response to the at least one interconnect lane being unavailable.

18. A network device, comprising:

one or more circuits configured to:

provide data across a first set of interconnect lanes;

in response to receiving a power reduction message to enable power saving, determine that at least one interconnect lane among the first set of interconnect lanes is to be made unavailable; and

redistribute data to a second set of interconnect lanes, the second set not including the at least one interconnect lane.

19. The network device of claim 18 , further comprising:

a physical medium attachment (PMA) sublayer comprising components associated with the first set of interconnect lanes; and

a physical medium dependent (PMD) sublayer associated with the first set of interconnect lanes.

20. The network device of claim 18 , wherein the data is provided to a second network device via the first set of interconnect lanes, and wherein the power reduction message is received from the second network device.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE OF THE MERGER AND APPLICATION NOS. 13/237,550 AND 16/103,107 FROM THE MERGER PREVIOUSLY RECORDED ON REEL 047231 FRAME 0369. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 8, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048549/0113 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047231/0369 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 12, 2017
From: STONE, ROB; BADEN, ERIC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 042672/0843 →
Continuity (2)
Provisional Application 62309871 · Mar 17, 2016
Related Publication 20170272308A1 · Sep 21, 2017