Memory device

1. A memory device comprising:

a memory cell;

a data buffer which receives write data from an exterior;

a first latch circuit which latches data stored in the memory cell;

a second latch circuit which latches data transferred from the data buffer;

a controller which performs a first transfer operation to transfer data from the data buffer to the second latch circuit after a write command is received and then a first period elapses; and

a write circuit which performs a write operation to write data of the second latch circuit to the memory cell after the first transfer operation, when data of the first latch circuit is different from the data of the second latch circuit,

wherein the controller performs a second transfer operation to transfer data from the second latch circuit to the first latch circuit after the write operation,

wherein the first period is equal to or longer than a second period ranging from a start of the write operation to a finish of the second transfer operation, and

wherein the write circuit does not write the data of the second latch circuit to the memory cell, when the data of the first latch circuit is equal to the data of the second latch circuit.

2. The device of claim 1 , further comprising a generator which generates an enable signal asserted during the write operation,

wherein the controller performs the second transfer operation after the enable signal is negated.

3. The device of claim 1 , further comprising a comparator which compares the data of the first latch circuit with the data of the second latch circuit,

wherein the write circuit operates in accordance with a comparison result of the comparator.

4. The device of claim 3 , further comprising:

a first data line connecting the first latch circuit with a first input terminal of the comparator; and

a second data line connecting the second latch circuit with a second input terminal of the comparator.

5. The device of claim 1 , further comprising:

a sense amplifier which reads data of the memory cell; and

a third transfer gate which transfers the read data to the first latch circuit.

6. The device of claim 1 , wherein, when a second write command is received during the write operation for a first write command, the controller performs the first transfer operation for the second write command after the second transfer operation for the first write command.

7. The device of claim 1 , wherein, when a second write command is received during the second transfer operation for a first write command, the controller performs the first transfer operation for the second write command after the second transfer operation for the first write command.

8. The device of claim 1 , wherein, when a second write command is received during the first transfer operation for a first write command, the controller performs the first transfer operation for the second write command after the first transfer operation for the first write command.

9. The device of claim 1 , wherein the memory cell includes a variable resistive element.

10. The device of claim 1 , wherein the memory cell includes a magnetoresistive element.

11. The device of claim 1 , wherein the memory device is a spin-transfer torque magnetoresistive random access memory (STT-MRAM).

12. A memory device comprising:

a memory cell;

a data buffer which receives write data from an exterior;

a first latch circuit which latches data stored in the memory cell;

a second latch circuit which latches data transferred from the data buffer;

a controller which performs a first transfer operation to transfer data from the data buffer to the second latch circuit after a write command is received and then a first period elapses; and

a write circuit which performs a write operation to write data of the second latch circuit to the memory cell after the first transfer operation, when data of the first latch circuit is different from the data of the second latch circuit,

wherein the controller performs a second transfer operation to transfer data from the second latch circuit to the first latch circuit after the write operation,

wherein the first period is equal to or longer than a second period ranging from a start of the write operation to a finish of the second transfer operation,

wherein the memory device further comprises:

a first counter which counts the first period; and

a second counter which counts the second period, and

wherein the first counter is reset in response to the write command.

13. The device of claim 12 , wherein the second counter starts a count operation in response to a first signal from the first counter, after the first period lapses.

14. The device of claim 12 , wherein:

the first counter generates a second signal after the first period is counted, and

the controller performs the first transfer operation in response to the second signal.

15. A memory device comprising:

a memory cell;

a data buffer which receives write data from an exterior;

a first latch circuit which latches data stored in the memory cell;

a second latch circuit which latches data transferred from the data buffer;

a controller which performs a first transfer operation to transfer data from the data buffer to the second latch circuit after a write command is received and then a first period elapses; and

a write circuit which performs a write operation to write data of the second latch circuit to the memory cell after the first transfer operation, when data of the first latch circuit is different from the data of the second latch circuit,

wherein the controller performs a second transfer operation to transfer data from the second latch circuit to the first latch circuit after the write operation,

wherein the first period is equal to or longer than a second period ranging from a start of the write operation to a finish of the second transfer operation, and

wherein the memory device further comprises:

a first transfer gate connected between the data buffer and the second latch circuit; and

a second transfer gate connected between the second latch circuit and the first latch circuit.