Memory device
A memory device includes: a memory cell array including memory cells; a correction circuit which encodes write data and generates an error correction signal, in a first period; a write circuit which writes the write data to a memory cell in a second period following the first period; a first circuit which receives a first signal generated based on a write command, generates a first clock signal having a first cycle from the first signal, and sets the first period with the first clock signal; and a second circuit which receives the first clock signal, generates a second clock signal having a second cycle from the first clock signal, and sets the second period with the second clock signal.
1. A memory device comprising:
a memory cell array including memory cells;
a correction circuit encoding write data and generating an error correction signal, in a first period;
a write circuit writing the write data to a memory cell in a second period following the first period;
a first circuit receiving a first signal generated based on a write command, generating a first clock signal having a first cycle from the first signal, and setting the first period with the first clock signal; and
a second circuit receiving the first clock signal, generating a second clock signal having a second cycle from the first clock signal, and setting the second period with the second clock signal.
2. The device of claim 1 , wherein the second cycle is different from the first cycle.
3. The device of claim 1 , wherein
the first circuit includes a timer measuring the first cycle, and
the second circuit includes a timer measuring the second cycle.
4. The device of claim 1 , further comprising a generator generating a second signal asserted during the second period,
wherein the second signal is generated based on the first clock signal and the second clock signal, and
the write circuit performs a write operation based on the second signal.
5. The device of claim 1 , further comprising:
a generator generating a second signal asserted during the second period; and
a shift register including a first register and a second register connected in series,
wherein the first register outputs a third signal in accordance with a column signal to select the memory cell and the first clock signal,
the second register outputs a fourth signal in accordance with the column signal and the second clock signal,
the second signal is generated based on the third signal and the fourth signal, and
the write circuit performs a write operation based on the second signal.
6. The device of claim 1 , further comprising a nonvolatile memory storing first information and second information,
wherein the first circuit determines the first cycle based on the first information, and
the second circuit determines the second cycle based on the second information.
7. The device of claim 6 , wherein the nonvolatile memory is a fuse circuit.
8. The device of claim 1 , wherein each of the memory cells includes a variable resistive element.
9. The device of claim 1 , wherein each of the memory cells includes a magnetoresistive element.
10. The device of claim 1 , wherein the memory device is a spin-transfer torque magnetoresistive random access memory (STT-MRAM).
11. A memory device comprising:
a memory cell array including memory cells;
a first oscillator generating a first clock signal;
a second oscillator generating a second clock signal;
a first circuit counting the first clock signal, receiving a first signal generated based on a write command, and generating a second signal obtained by delaying the first signal by a first time;
a second circuit counting the second clock signal, receiving the second signal, and generating a third signal obtained by delaying the second signal by a second time;
a generator generating a fourth signal asserted from the second signal to the third signal; and
a write circuit writing data to a memory cell based on the fourth signal.
12. The device of claim 11 , wherein
each of the memory cells includes a magnetoresistive element,
the magnetoresistive element includes a first magnetic layer with a variable magnetization direction, a second magnetic layer with an invariable magnetization direction, and a nonmagnetic layer provided between the first magnetic layer and the second magnetic layer, and
the first time is set in accordance with a recovery time of the second magnetic layer.
13. The device of claim 11 , wherein the second clock signal has a cycle different from a cycle of the first clock signal.
14. The device of claim 11 , further comprising a nonvolatile memory storing first information and second information,
wherein the first circuit determines a cycle of the first clock signal based on the first information, and
the second circuit determines a cycle of the second clock signal based on the second information.
15. The device of claim 14 , wherein the nonvolatile memory is a fuse circuit.
16. The device of claim 11 , wherein each of the memory cells includes a variable resistive element.
17. The device of claim 11 , wherein each of the memory cells includes a magnetoresistive element.
18. The device of claim 11 , wherein the memory device is a spin-transfer torque magnetoresistive random access memory (STT-MRAM).