Reflection type phase shifter with active device tuning

1. A phase shifter, comprising:

first and second RF terminals;

a reference potential terminal;

a lumped element LC network connected to the first and second RF terminals and the reference potential terminal;

first and second active semiconductor devices to the lumped element LC network and to the reference potential terminal, each of the first and second active semiconductor devices comprising a control terminal and first and second output terminals; and

a second independent voltage terminal connected to the first output terminals of the first and second active semiconductor devices;

wherein the lumped element LC network presents a reactance across the first and second RF terminals that shifts the phase of an RF signal as between the first and second RF terminals, and

wherein the first and second active semiconductor devices are configured to tune the phase shift of the RF signal by controlling the reactance across the first and second RF terminals,

wherein an impedance of the first and second active semiconductor devices is independently controllable via an independent voltage applied to the second voltage terminal.

2. The phase shifter of claim 1 , wherein the lumped element LC network comprises:

a first series branch comprising a capacitive element connected in series between the first RF terminal and the first output terminal of the first active semiconductor device;

a second series branch comprising a capacitive element connected in series between the second RF terminal and the first output terminal of the second active semiconductor device; and

a first parallel branch comprising a first inductive element connected between the first series branch and the reference potential terminal and a second inductive element connected between the second series branch and the reference potential terminal.

3. The phase shifter of claim 2 , wherein the lumped element LC network further comprises second and third parallel branches, wherein each of the first, second and third parallel branches comprise:

a first inductor directly connected between the first series branch and the reference potential terminal;

a first capacitor directly connected between the first and second series branches; and

a second inductor directly connected between the second series branch and the reference potential terminal.

4. The phase shifter of claim 3 , wherein each of the first and second series branches comprise:

a first capacitor directly connected between the first parallel branch and the second parallel branch; and

a second capacitor directly connected between the second and third parallel branches.

5. The phase shifter of claim 4 , further comprising:

a first independent voltage terminal connected to the control terminals of the first and second active semiconductor devices.

6. The phase shifter of claim 5 , wherein the phase shifting circuit further comprises:

first and second RF chokes directly electrically connected between the first independent voltage terminal and the control terminals of the first and second active semiconductor devices, respectively;

third and fourth RF chokes directly electrically connected between the second independent voltage terminal and the first output terminals of the first and second active semiconductor devices, respectively; and

first and second DC blocking capacitors directly electrically connected between the first output terminals of the first and second active semiconductor devices and the second capacitor of the first and second series branches, respectively.

7. The phase shifter of claim 1 , wherein the first and second active semiconductor devices comprise MOSFET devices.

8. The phase shifter of claim 7 , wherein the first and second active semiconductor devices are LDMOS devices.

9. The phase shifter of claim 1 , wherein the phase shifter is configured to electrically isolate a DC signal applied to the second independent voltage terminal from the lumped element DC network and to apply the electrically isolated DC signal to the first output terminals of the first and second active semiconductor devices.

10. The phase shifter of claim 9 , wherein the phase shifter further comprises:

first and second DC blocking capacitors electrically connected between the first output terminals of the first and second active semiconductor devices and the second capacitor of the first and second series branches, respectively; and

third and fourth RF chokes electrically connected between the second independent voltage terminal and the first output terminals of the first and second active semiconductor devices.

11. A phase shifter, comprising:

first and second RF terminals;

a reference potential terminal;

a lumped element LC network connected to the first and second RF terminals and the reference potential terminal;

first and second active semiconductor devices connected to the lumped element LC network and to the reference potential terminal, each of the first and second active semiconductor devices comprising a control terminal and first and second output terminals,

wherein the lumped element LC network presents a reactance across the first and second RF terminals that shifts the phase of an RF signal as between the first and second RF terminals, and

wherein the first and second active semiconductor devices are configured to tune the phase shift of the RF signal by controlling the reactance across the first and second RF terminals,

wherein the lumped element LC network comprises:

a first series branch comprising a capacitive element connected in series between the first RF terminal and the first output terminal of the first active semiconductor device;

a second series branch comprising a capacitive element connected in series between the second RF terminal and the first output terminal of the second active semiconductor device;

a first parallel branch comprising a first inductive element connected between the first series branch and the reference potential terminal and a second inductive element connected between the second series branch and the reference potential terminal; and

second and third parallel branches,

wherein each of the first, second and third branches comprise:

a first inductor directly connected between the first series branch and the reference potential terminal;

a first capacitor directly connected between the first and second series branches; and

a second inductor directly connected between the second series branch and the reference potential terminal.