IP Library Granted Patent US 10,056,838
Granted Patent B2
US 10,056,838 · App. 15/461,543 · Granted Aug 21, 2018

Circuit and method for reducing analog buck current control loop sensitivity to supply path resistance

Inventor: Shafqat Ali (Graz, AT)
Assignee: Dialog Semiconductor (UK) Limited
H02M3/158G05F1/575
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Quick Facts
Patent No.
US 10,056,838
App. No.
15/461,543
Granted
Aug 21, 2018
Kind
B2
Abstract

This application relates to a power converter circuit for converting a supply voltage received at an input node and providing, at an output node, a current at the converted supply voltage. The power converter circuit contains a DC-DC converter circuit for generating the current at the output node under control of a control signal, a current sensing circuit for sensing a current indicative of a current at the input node, a voltage adjustment circuit for sensing a voltage indicative of the supply voltage and generating an adjusted voltage on the basis of the sensed voltage and the sensed current, and an error amplifier stage for generating the control signal on the basis of the adjusted voltage and a reference voltage. The application further relates to a method of operating such power converter circuit.

Claims (24)

1. A power converter circuit for converting an input voltage received at an input node and providing, at an output node, a current at the converted voltage, the power converter circuit comprising:

a DC-DC converter circuit for generating the current at the output node under control of a control signal, wherein the DC-DC converter circuit is controlled by the control signal to reduce the current at the input node if there is a drop in the input voltage;

a current sensing circuit for sensing a current indicative of a current at the input node;

a voltage adjustment circuit for sensing a voltage indicative of the input voltage and generating an adjusted voltage on the basis of the sensed voltage and the sensed current; and

an error amplifier stage for generating the control signal on the basis of the adjusted voltage and a reference voltage,

wherein the adjusted voltage is generated by adding a portion of the sensed current, after conversion to a voltage domain, to the sensed voltage, so that a loop gain of a control loop for the current at the input node has reduced sensitivity to an input resistance of a supply path that is connected to the input node and supplies the input voltage.

2. The power converter circuit according to claim 1 , wherein the voltage adjustment circuit is configured to scale the sensed current.

3. The power converter circuit according to claim 1 , wherein the voltage adjustment circuit comprises a controllable current sink for sinking, from a voltage level of the input voltage, a sink current that depends on the sensed current.

4. The power converter circuit according to claim 3 , wherein the voltage adjustment circuit comprises an impedance for passing the sink current through the impedance.

5. The power converter circuit according to claim 4 , wherein the voltage adjustment circuit comprises a circuit branch coupled between the voltage level of the input voltage and ground, the circuit branch comprising the impedance and the controllable current sink coupled in series.

6. The power converter circuit according to claim 1 , further comprising:

a reference adjustment circuit for generating the reference voltage on the basis of the sensed voltage and a fixed reference voltage.

7. A power conversion method of converting an input voltage and providing an output current at the converted voltage, the method comprising:

performing DC-DC conversion under control of a control signal, for generating the output current, the DC-DC conversion is controlled by the control signal to reduce an input current if there is a drop in the input voltage;

sensing a current indicative of the input current;

sensing a voltage indicative of the input voltage;

generating an adjusted voltage on the basis of the sensed voltage and the sensed current; and

generating the control signal on the basis of a difference between the adjusted voltage and a reference voltage,

wherein the adjusted voltage is generated by adding a portion of the sensed current, after conversion to a voltage domain, to the sensed voltage, so that a loop gain of a control loop for the input current has reduced sensitivity to an input resistance of a supply path that supplies the input voltage.

8. The power conversion method according to claim 7 , wherein generating the adjusted voltage involves scaling the sensed current.

9. The power conversion method according to claim 7 , wherein generating the adjusted voltage involves sinking, from a voltage level of the input voltage, a sink current that depends on the sensed current.

10. The power conversion method according to claim 9 , wherein generating the adjusted voltage involves passing the sink current through an impedance coupled between the voltage level of the input voltage and a controllable current sink that sinks the sink current.

11. The power conversion method according to claim 7 , further comprising:

generating the reference voltage on the basis of the sensed voltage and a fixed reference voltage.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 29, 2019
From: DIALOG SEMICONDUCTOR (UK) LIMITED
To: APPLE INC.
Reel/Frame 049018/0674 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 25, 2017
From: ALI, SHAFQAT
To: DIALOG SEMICONDUCTOR (UK) LIMITED
Reel/Frame 042138/0403 →
Priority Claims (1)
DE 10 2016 204 974 · Mar 24, 2016 · national
Continuity (1)
Related Publication 20170277212A1 · Sep 28, 2017