Semiconductor memory device
A semiconductor memory device includes a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof, a circuit provided on the substrate around the memory plane, a first insulating layer including a first portion and a second portion between the substrate and a second insulating layer, and the second insulating layer covering the circuit. The first portion is provided along an outer edge of the memory plane, and the second portion is spaced from the first portion and is provided on the circuit side. The second insulating layer includes a part in contact with the substrate between the first portion and the second portion, and the second insulating layer blocks a diffusion of hydrogen radicals with a higher rate than the first insulating layer.
1. A semiconductor memory device comprising:
a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof;
a circuit provided on the substrate around the memory plane;
a first insulating layer comprising a first portion and a second portion between the substrate and a second insulating layer, the first portion being provided along an outer edge of the memory plane, and the second portion being spaced from the first portion and being provided on the circuit side; and
the second insulating layer covering the circuit,
the second insulating layer including a part in contact with the substrate between the first portion and the second portion, and
the second insulating layer blocking a diffusion of hydrogen radicals with a higher rate than the first insulating layer.
2. The semiconductor memory device according to claim 1 ,
wherein the first insulating layer includes silicon oxide, and
the second insulating layer includes silicon nitride.
3. The semiconductor memory device according to claim 1 ,
wherein the substrate has a well of a first conductivity type, the memory plane is provided on the well, and the first insulating layer is in contact with a surface of the well.
4. The semiconductor memory device according to claim 1 ,
wherein the circuit includes a transistor having a source/drain region and a gate electrode, and the first insulating layer covers the source/drain region and the gate electrode.
5. The semiconductor memory device according to claim 1 ,
wherein the second insulating layer includes a part in contact with the substrate, the part of the second insulating layer extending along a boundary between the memory plane and a region on which the circuit is provided on the substrate.
6. The semiconductor memory device according to claim 1 ,
wherein the memory plane is disposed inside a circuit region, the circuit being provided in the circuit region, and
the second insulating layer includes a part in contact with the substrate, the part of the second insulating layer extending along a boundary between the circuit region and the memory plane, and surrounding the memory plane.
7. The semiconductor memory device according to claim 1 ,
wherein the second insulating layer includes a part in contact with the substrate, the part of the second insulating layer surrounding a region in which the circuit is provided on the substrate.
8. The semiconductor memory device according to claim 1 , further comprising a third insulating layer provided on the second insulating layer and including a material same as the second insulating layer.
9. A semiconductor memory device comprising:
a memory plane including a plurality of electrode layers stacked on a substrate and a semiconductor layer extending through the plurality of electrode layers in a stacking direction thereof;
a circuit provided on the substrate around the memory plane; and
a silicon nitride layer covering the circuit,
the silicon nitride layer having a part extending along a boundary between a circuit region and the memory plane, the circuit being provided in the circuit region, and the silicon nitride layer being in contact with the substrate.
10. The semiconductor memory device according to claim 9 ,
wherein the part of the silicon nitride layer in contact with the substrate surrounds the memory plane on the substrate.
11. The semiconductor memory device according to claim 9 ,
wherein the part of the silicon nitride layer in contact with the substrate surrounds the circuit region on the substrate.
12. The semiconductor memory device according to claim 9 , further comprising:
a silicon oxide layer provided between the substrate and the silicon nitride layer, and including a first portion on the memory plane side and a second portion on the circuit side, the second portion being separated from the first portion,
the silicon nitride layer being in contact with the substrate between the first portion and the second portion.
13. The semiconductor memory device according to claim 9 , wherein the substrate includes a source layer provided on the memory plane side, and the silicon nitride layer is in contact with the source layer.
14. The semiconductor memory device according to claim 9 , wherein the circuit includes a transistor having a source/drain region and a gate electrode, and the silicon nitride layer covers the source/drain region and the gate electrode.