IP Library Granted Patent US 10,243,052
Granted Patent B2
US 10,243,052 · App. 15/463,137 · Granted Mar 26, 2019

Semiconductor memory device and method for manufacturing the same

Inventor: Jun Nishimura (Kuwana, JP)
Assignee: TOSHIBA MEMORY CORPORATION
H01L29/408H01L27/11565H01L27/11582
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Quick Facts
Patent No.
US 10,243,052
App. No.
15/463,137
Granted
Mar 26, 2019
Kind
B2
Abstract

According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor portion, and an insulating portion. The insulating portion is provided in the stacked body and extends in a stacking direction and a first direction along a surface of the substrate, the first direction crossing the stacking direction. The insulating portion includes a first insulating film containing silicon oxide, a second insulating film containing silicon oxide, and a third insulating film located between the first insulating film and the second insulating film and containing silicon nitride.

Claims (29)

1. A semiconductor memory device, comprising:

a substrate;

a stacked body provided on the substrate and including a plurality of electrode layers separately stacked each other;

a semiconductor portion provided in the stacked body and extending in a stacking direction of the plurality of electrode layers;

a charge storage film provided between the semiconductor portion and the stacked body;

an insulating portion provided in the stacked body and extending in the stacking direction and a first direction along a surface of the substrate, the first direction crossing the stacking direction, the insulating portion including a first insulating film containing silicon oxide, a second insulating film containing silicon oxide, and a third insulating film located between the first insulating film and the second insulating film and containing silicon nitride; and

an insulating layer provided on the stacked body and the insulating portion and containing silicon nitride,

the first insulating film including a first side portion extending in the stacking direction and a first bottom portion connected to the first side portion,

the first side portion of the first insulating film being located on a side surface of the third insulating film,

a lower end of the third insulating film being located on the first bottom portion of the first insulating film, and

the first bottom portion of the first insulating film and the third insulating film being located on a side surface of the second insulating film.

2. The device according to claim 1 , wherein

a shape of the insulating portion is a plate shape, and

a shape of the first insulating film is an L shape when viewed from the first direction.

3. A semiconductor memory device, comprising:

a substrate;

a stacked body provided on the substrate and including a plurality of electrode layers separately stacked each other, the electrode layers extending in a first direction along a surface of the substrate;

a semiconductor portion provided in the stacked body and extending in a stacking direction of the plurality of electrode layers;

an interconnect portion provided in the stacked body and extending in the first direction and the stacking direction;

an insulating portion provided on a side surface of the interconnect portion, extending in the stacking direction and the first direction, and including a first insulating film, a second insulating film and a third insulating film, the first insulating film containing silicon oxide, the second insulating film containing silicon oxide and located on a side surface of the interconnect portion, the third insulating film containing silicon nitride and located between the first insulating film and the second insulating film; and

an insulating layer provided on the stacked body and the insulating portion and containing silicon nitride,

the first insulating film including a first side portion extending in the stacking direction and a first bottom portion connected to the first side portion,

the first side portion of the first insulating film being located on a side surface of the third insulating film,

a lower end of the third insulating film being located on the first bottom portion of the first insulating film, and

the first bottom portion of the first insulating film and the third insulating film being located on a side surface of the second insulating film.

4. The device according to claim 3 , wherein

a shape of the insulating portion is a plate shape, and

a shape of the first insulating film is an L shape when viewed from the first direction.

5. The device according to claim 3 , further comprising a charge storage film provided around the semiconductor portion.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 27, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043355/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 27, 2017
From: NISHIMURA, JUN
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 042163/0604 →
Continuity (2)
Provisional Application 62394459 · Sep 14, 2016
Related Publication 20180076293A1 · Mar 15, 2018