Biasing the substrate region of an MOS transistor
An integrated electronic device is supported by a substrate of a silicon on insulator type. At least one transistor is formed in and on a semiconductor film of the substrate. The transistor includes a drain region and a source region of a first conductivity type and a substrate (body) region of a second conductivity type lying under a gate region. An extension region laterally continues the substrate (body) region beyond the source and drain regions and borders, in contact with, the source region through a border region having the first conductivity type. This supports formation of an electrical connection of the source region and the substrate (body) region.
1. An integrated electronic device, comprising:
a substrate of a silicon on insulator type having a semiconductor film arranged on a buried insulating layer, and
at least one transistor arranged in and on the semiconductor film,
wherein said at least one transistor includes:
a drain region and a source region of a first conductivity type,
a film region of a second conductivity type and lying under a gate region of said at least one transistor,
contacting zones on the source, gate and drain regions, and
an extension region laterally continuing the film region beyond the source and drain regions and bordering, in contact with, the source region by a border region having the first conductivity type so as to electrically couple the source region and the film region.
2. The device according to claim 1 , wherein the extension region comprises a connecting part of a same conductivity type as the film region that connects the film region to the border region, and an electrically conductive region at least partially covering the film region and the connecting part.
3. The device according to claim 2 , wherein the electrically conductive region comprises a metal silicide having a resistivity of less than 5×10 −5 ohm-centimeters.
4. The device according to claim 2 , wherein the connecting part has a first portion laterally continuing the film region and a second portion extending perpendicularly to the first portion and contacting the border region.
5. The device according to claim 4 , wherein said at least one transistor comprises a pair of transistors, wherein a second portion of the connecting part of each transistor of said pair of transistors extending towards one another from the respective first portion so as to form a common second connecting portion, the device further comprising a common border region between transistors of said pair of transistors, said common border region extending from the common second connecting portion and bordering, in contact, the source region of each transistor of the pair of transistors so as to electrically couple the source region of each transistor of the pair of transistors and the film region of each transistor of the pair of transistors.
6. The device according to claim 1 , wherein said at least one transistor comprises a pair of transistors, where the gate region of each transistor of the pair of transistors is mutually electrically coupled by a gate material line extending perpendicularly to the gate regions of the transistors.
7. The device according to claim 1 , wherein said at least one transistor comprises a pair of transistors, where the gate region of each transistor of the pair of transistors is mutually electrically coupled by a pair of gate material lines extending perpendicularly to the gate regions of the transistors, said pair of gate materials lines being located on opposite sides of each transistor.
8. The device according to claim 1 , wherein the substrate is of a partially depleted silicon on insulator type.
9. An integrated electronic device, comprising:
a transistor having a source region, a drain region and a body region within a semiconductor layer of a silicon on insulator (SOI) substrate, said body region positioned between the source region and drain region with a first side of the source region facing said body region,
a border region within said semiconductor layer and in contact with the source region, with a second side of the source region, opposite to said first side, facing said border region; and
a connecting region within said semiconductor layer in contact at a first end with the body region and further in contact at a second end with the border region;
wherein said source region and border region are doped with a first conductivity type and said body region and connecting region are doped with a second conductivity type; and
an electrical connection in contact with both at least a portion of the connecting region and at least a portion of the border region.
10. The device of claim 9 , wherein the portion of the connecting region is more heavily doped than the body region.
11. The device of claim 9 , wherein the portion of the border region is more heavily doped than a remaining portion of the border region adjacent the source region.
12. The device of claim 9 , wherein the electrical connection is a metal silicide having a resistivity of less than 5×10 −5 ohm-centimeters.
13. The device of claim 9 , wherein said body region, source region and border region have longer sides extending parallel to each other in a first direction, and wherein said connecting region has a longer side extending in a second direction perpendicular to said first direction.
14. An integrated electronic device, comprising:
a first transistor having a first source region, a first drain region and a first body region within a semiconductor layer of a silicon on insulator (SOI) substrate, said first body region positioned between the first source region and first drain region with a first side of the first source region facing said first body region,
a second transistor having a second source region, a second drain region and a second body region within the SOI substrate, said second body region positioned between the second source region and second drain region with a first side of the second source region facing said second body region,
a border region within said semiconductor layer and in contact each of the first and second source regions, with a second side of each of the first and second source regions, opposite to said first sides, facing said border region; and
a connecting region within said semiconductor layer in contact at a first end with the first body region, in contact at a second end with the second body and further in contact at a middle with the border region;
wherein said first and second source regions and said border region are doped with a first conductivity type and said first and second body regions and connecting region are doped with a second conductivity type; and
an electrical connection in contact with both at least a portion of the connecting region and at least a portion of the border region.
15. The device of claim 14 , wherein the portion of the connecting region is more heavily doped than the first and second body regions.
16. The device of claim 14 , wherein the portion of the border region is more heavily doped than a remaining portion of the border region adjacent the first and second source regions.
17. The device of claim 14 , wherein the electrical connection is a metal silicide having a resistivity of less than 5×10 −5 ohm-centimeters.
18. The device of claim 14 , wherein said first and second body regions, first and second source regions and border region have longer sides extending parallel to each other in a first direction, and wherein said connecting region has a longer side extending in a second direction perpendicular to said first direction.