Sequence triggering in RF front-ends

1. Sequence trigger circuitry configured to repeat command sequences to switch between a plurality of communication modes of a radio frequency front end (RFFE), the sequence trigger circuitry comprising:

a first logic circuitry configured to:

in response to a trigger signal, generate a first output signal or a second output signal to activate a first command sequence or a second command sequence, respectively;

a second logic circuitry configured to:

activate a third command sequence based on a comparison of a clock output signal with a first timer value and upon generating the first output signal, wherein the first command sequence and the third command sequence switch the RFFE into a receive mode of the plurality of communication modes; and

a third logic circuitry configured to:

activate a fourth command sequence based on a comparison of the clock output signal with a second timer value and upon generating the second output signal, wherein the second command sequence and the fourth command sequence switch the RFFE into a transmit mode of the plurality of communication modes.

2. The sequence trigger circuitry of claim 1 , wherein:

the first logic circuitry comprises a flip-flop; and

the second logic circuitry and the third logic circuitry are comparators.

3. The sequence trigger circuitry of claim 1 , wherein the first logic circuitry is configured to:

enable the second logic circuitry via the first output signal; and

enable the third logic circuitry via the second output signal.

4. The sequence trigger circuitry of claim 1 , further comprising:

counter circuitry configured to:

receive a clock signal input and the trigger signal; and

generate the clock output signal in response to the clock signal input.

5. The sequence trigger circuitry of claim 1 , wherein the first logic circuitry is configured to:

receive the trigger signal during the receive mode of the RFFE; and

generate the second output signal to:

activate the second command sequence to disable a low-noise amplifier (LNA) of the RFFE; and

enable the second comparator.

6. The sequence trigger circuitry of claim 5 , wherein the third logic circuitry is configured to, upon the clock output signal reaching the second timer value, activate the fourth command sequence to:

enable a power amplifier (PA) of the RFFE; and

switch the RFFE to the transmit mode.

7. The sequence trigger circuitry of claim 1 , wherein the first logic circuitry is configured to:

receive the trigger signal during a data transmission mode of the RFFE; and

generate the first output signal to:

activate the first command sequence to disable a power amplifier (PA) of the RFFE;

switch the RFFE to the receive mode; and

enable the second logic circuitry.

8. The sequence trigger circuitry of claim 7 , wherein the second logic circuitry is configured to:

upon the clock output signal reaching the first timer value, activate the third command sequence to enable a low-noise amplifier (LNA) of the RFFE.

9. The sequence trigger circuitry of claim 1 , wherein the first logic circuitry is configured to:

receive the trigger signal during a receive only mode of the RFFE; and

generate the second output signal to:

activate the second command sequence to disable a low-noise amplifier (LNA) of the RFFE; and

enable the third logic circuitry.

10. The sequence trigger circuitry of claim 9 , wherein the third logic circuitry is configured to, upon the clock output signal reaching the second timer value, activate the fourth command sequence to:

disable a power amplifier (PA) of the RFFE; and

switch the RFFE to idle mode.

11. The sequence trigger circuitry of claim 10 , wherein the first logic circuitry is configured to:

receive a second trigger signal while in the idle mode;

reset the clock output signal; and

generate the first output signal to:

activate the first command sequence to disable the PA of the RFFE; and

enable the second logic circuitry.

12. The sequence trigger circuitry of claim 11 , wherein the second logic circuitry is configured to, upon the clock output signal reaching the first timer value, activate the third command sequence to:

enable the LNA of the RFFE; and

resume the receive only mode.

13. The sequence trigger circuit of claim 1 , wherein the first logic circuitry is configured to:

receive the trigger signal during a transmit only mode of the RFFE; and

generate the first output signal to:

activate the first command sequence to disable a power amplifier (PA) of the RFFE; and

enable the second logic circuitry.

14. The sequence trigger circuit of claim 13 , wherein the second logic circuitry is configured to, upon the clock output signal reaching the first timer value, activate the third command sequence to:

disable a low-noise amplifier (LNA) of the RFFE; and

switch the RFFE to idle mode.

15. The sequence trigger circuitry of claim 14 , wherein the first logic circuitry is configured to:

receive a second trigger signal while in the idle mode;

reset the clock output signal; and

generate the second output signal to:

activate the second command sequence to disable the LNA of the RFFE; and

enable the third logic circuitry.

16. The sequence trigger circuitry of claim 15 , wherein the third logic circuitry is configured to, upon the clock output signal reaching the second timer value, activate the fourth command sequence to:

enable the PA of the RFFE; and

resume the transmit only mode.

17. A radio frequency (RF) front end (RFFE) apparatus, comprising:

a low-noise amplifier (LNA) configured to amplify a first RF signal for processing by baseband circuitry, the first RF signal received during a receive mode of the RFFE;

a power amplifier (PA) configured to amplify a second RF signal output by the baseband circuitry for transmission during a transmit mode of the RFFE, the PA being different than the LNA;

sequence trigger circuitry coupled to the LNA and the PA, the sequence trigger circuitry comprising a plurality of registers and configured to:

in response to a first trigger signal:

activate a first command sequence stored in a first register of the plurality of registers to disable the PA and switch the RFFE to the receive mode; and

activate a second command sequence stored in a second register of the plurality of registers to enable the LNA to process RF signals received during the receive mode; and

in response to a second trigger signal:

activate a third command sequence stored in a third register of the plurality of registers to disable the LNA; and

activate a fourth command sequence stored in a fourth register of the plurality of registers to enable the PA and switch the RFFE to the transmit mode;

a first logic circuit configured to:

in response to the first trigger signal, generate a first output signal to activate the first command sequence to disable the PA and switch the RFFE to the receive mode; and

in response to the second trigger signal, generate a second output signal to activate the third command sequence to disable the LNA; and

a second logic circuitry configured to:

activate the second command sequence based on a comparison of a clock output signal with a first timer value and upon generating the first output signal.

18. The RFFE circuit of claim 17 , wherein the sequence trigger circuitry further comprises:

a third logic circuitry configured to:

activate the fourth command sequence based on a comparison of the clock output signal with a second timer value and upon generating the second output signal.