Semiconductor memory device
A semiconductor memory device according to an embodiment includes: a first wiring line extending in a first direction; a second wiring line extending in a second direction, the second direction intersecting the first direction; a variable resistance film disposed at an intersection of the first wiring line and the second wiring line; a channel body disposed at a first end of the first wiring line; a third wiring line electrically connected to the first wiring line via the channel body; and a gate wiring line extending in the first direction and facing the channel body from the second direction.
1. A semiconductor memory device, comprising
a first wiring line extending in a first direction;
a second wiring line extending in a second direction, the second direction intersecting the first direction;
a variable resistance film disposed at an intersection of the first wiring line and the second wiring line;
a channel body disposed at a first end of the first wiring line;
a third wiring line electrically connected to the first wiring line via the channel body;
a gate wiring line extending in the first direction and facing the channel body from the second direction; and
a plurality of the first wiring lines aligned in the second direction,
wherein the gate wiring line is disposed between the plurality of first wiring lines in the second direction.
2. The semiconductor memory device according to claim 1 , comprising
a plurality of the second wiring lines aligned in a third direction, the third direction intersecting the first direction and the second direction,
wherein the gate wiring line is disposed between the plurality of second wiring lines in the third direction.
3. The semiconductor memory device according to claim 2 , wherein
a plurality of the gate wiring lines are arranged in a matrix in the second direction and the third direction,
the plurality of gate wiring lines are electrically commonly connected every column, and
a column direction of the commonly connected gate wiring lines intersects an extension direction of the third wiring line.
4. The semiconductor memory device according to claim 1 , wherein
a plurality of the gate wiring lines are arranged in the second direction, and
the semiconductor memory device further comprises a fourth wiring line electrically commonly connected to one ends of the plurality of gate wiring lines.
5. The semiconductor memory device according to claim 4 , wherein
the fourth wiring line extends in the second direction and intersects the third wiring line.
6. A semiconductor memory device, comprising:
a first wiring line extending in a first direction;
a second wiring line extending in a second direction, the second direction intersecting the first direction;
a variable resistance film disposed at an intersection of the first wiring line and the second wiring line;
a channel body disposed at a first end of the first wiring line;
a third wiring line electrically connected to the first wiring line via the channel body; and
a gate wiring line extending in the first direction and facing the channel body from the second direction; wherein
the gate wiring line is a columnar body extending from a position of a second end different from the first end of the first wiring line to a position of the channel body, in the first direction.
7. The semiconductor memory device according to claim 6 , further comprising
an insulating film covering a side surface of the gate wiring line.
8. The semiconductor memory device according to claim 6 , wherein
the first direction is a direction intersecting an upper surface of a semiconductor substrate.
9. The semiconductor memory device according to claim 8 , wherein
the third wiring line is disposed further from the semiconductor substrate than the second wiring line is, in the first direction.
10. A semiconductor memory device, comprising:
a semiconductor substrate;
a first wiring line including a first channel body that extends in a first direction intersecting an upper surface of the semiconductor substrate;
a second wiring line extending in a second direction, the second direction intersecting the first direction;
a variable resistance film disposed at an intersection of the first wiring line and the second wiring line;
a second channel body disposed at a first end of the first wiring line;
a third wiring line electrically connected to the first wiring line via the second channel body;
a first gate wiring line extending in the first direction and facing the first channel body from the second direction; and
a second gate wiring line extending in the first direction and facing the second channel body from the second direction.
11. The semiconductor memory device according to claim 10 , comprising
a plurality of the first wiring lines aligned in the second direction,
wherein the second gate wiring line is disposed between the plurality of first wiring lines in the second direction.
12. The semiconductor memory device according to claim 11 , comprising
a plurality of the second wiring lines aligned in a third direction, the third direction intersecting the first direction and the second direction,
wherein the second gate wiring line is disposed between the plurality of second wiring lines in the third direction.
13. The semiconductor memory device according to claim 11 , wherein
a plurality of the second gate wiring lines are arranged in a matrix in the second direction and a third direction, the third direction intersecting the first direction and the second direction,
the plurality of second gate wiring lines are electrically commonly connected every column, and
a column direction of the commonly connected second gate wiring lines intersects an extension direction of the third wiring line.
14. The semiconductor memory device according to claim 10 , wherein
a plurality of the second gate wiring lines are arranged in the second direction, and
the semiconductor memory device further comprises a fourth wiring line electrically commonly connected to one ends of the plurality of second gate wiring lines.
15. The semiconductor memory device according to claim 14 , wherein
the fourth wiring line extends in the second direction and intersects the third wiring line.
16. The semiconductor memory device according to claim 14 , wherein
the fourth wiring line is disposed closer to the semiconductor substrate than the second wiring line is, in the first direction.
17. The semiconductor memory device according to claim 10 , wherein
the second gate wiring line is integrated with the first gate wiring line.
18. The semiconductor memory device according to claim 10 , wherein
the second gate wiring line is separated from the first gate wiring line.
19. The semiconductor memory device according to claim 10 , further comprising
an insulating film covering a side surface of the second gate wiring line.