Direct memory access between an accelerator and a processor using a coherency adapter
View Patent ↗Direct memory access between an accelerator and a processor using a coherency adapter including receiving, by the adapter from the accelerator, a request to initiate a DMA transfer; providing, by the adapter, a translation tag (‘XTAG’) to the accelerator; receiving, by the adapter from the accelerator, a DMA instruction comprising the XTAG; generating, by the adapter, a DMA instruction comprising a real address based on the XTAG; and sending, by the adapter, the generated DMA instruction comprising the real address to a communications bus.
1. A method of direct memory access (‘DMA’) between a processor and an accelerator, the processor coupled to the accelerator by an adapter the method comprising:
providing, by the adapter, a translation tag (‘XTAG’) to the accelerator;
receiving, by the adapter from the accelerator, a DMA instruction comprising the XTAG; and
generating, by the adapter, a DMA instruction comprising a real address based on the XTAG.
2. The method of claim 1 , wherein providing, by the adapter, the XTAG to the accelerator is carried out in response to receiving a request to initiate a DMA transfer and comprises:
determining, by the adapter, the real address for the DMA transfer using the request; and
storing the real address in an XTAG table on the adapter, wherein the XTAG table maps the real address to the XTAG.
3. The method of claim 2 , wherein generating, by the adapter, the DMA instruction comprising the real address based on the XTAG comprises:
obtaining, from the XTAG table, the real address mapped to the XTAG; and
replacing, by the adapter, the XTAG in the DMA instruction with the real address.
4. The method of claim 2 , wherein the request to initiate the DMA transfer comprises an effective address, and wherein determining, by the adapter, the real address for the DMA transfer using the request comprises translating the effective address to the real address.
5. The method of claim 1 , further comprising receiving a request to initiate a DMA transfer via a coherency interface, and wherein the DMA instruction comprising the XTAG is received via a DMA interface.
6. The method of claim 5 , wherein the coherency interface is part of a coherency service layer on the adapter, and wherein the DMA interface is part of a DMA layer on the adapter.
7. The method of claim 1 , wherein the communications bus operatively couples the adapter to the processor.
8. An adapter for direct memory access (‘DMA’) between a processor and an accelerator, the processor coupled to the accelerator by the adapter, the adapter configured to carry out the steps of:
providing a translation tag (‘XTAG’) to the accelerator;
receiving, from the accelerator, a DMA instruction comprising the XTAG; and
generating a DMA instruction comprising a real address based on the XTAG.
9. The adapter of claim 8 , wherein providing the XTAG to the accelerator is carried out in response to receiving a request to initiate a DMA transfer and comprises:
determining the real address for the DMA transfer using the request; and
storing the real address in an XTAG table on the adapter, wherein the XTAG table maps the real address to the XTAG.
10. The adapter of claim 9 , wherein generating the DMA instruction comprising the real address based on the XTAG comprises:
obtaining, from the XTAG table, the real address mapped to the XTAG; and
replacing the XTAG in the DMA instruction with the real address.
11. The adapter of claim 9 , wherein the request to initiate the DMA transfer comprises an effective address, and wherein determining the real address for the DMA transfer using the request comprises translating the effective address to the real address.
12. The adapter of claim 8 , wherein the adapter is further configured to carry out the step of receiving a request to initiate a DMA transfer via a coherency interface, and wherein the DMA instruction comprising the XTAG is received via a DMA interface.
13. The adapter of claim 12 , wherein the coherency interface is part of a coherency service layer on the adapter, and wherein the DMA interface is part of a DMA layer on the adapter.
14. The adapter of claim 8 , wherein the communications bus operatively couples the adapter to the processor.
15. A computer program product for direct memory access (‘DMA’) between a processor and an accelerator, the processor coupled to the accelerator by an adapter, the computer program product disposed upon a computer readable medium, the computer program product comprising computer program instructions that, when executed, cause the adapter to carry out the steps of:
providing, by the adapter, a translation tag (‘XTAG’) to the accelerator;
receiving, by the adapter from the accelerator, a DMA instruction comprising the XTAG; and
generating, by the adapter, a DMA instruction comprising a real address based on the XTAG.
16. The computer program product of claim 15 , wherein providing, by the adapter, the XTAG to the accelerator is carried out in response to receiving a request to initiate a DMA transfer and comprises:
determining, by the adapter, the real address for the DMA transfer using the request; and
storing the real address in an XTAG table on the adapter, wherein the XTAG table maps the real address to the XTAG.
17. The computer program product of claim 16 , wherein generating, by the adapter, the DMA instruction comprising the real address based on the XTAG comprises:
obtaining, from the XTAG table, the real address mapped to the XTAG; and
replacing, by the adapter, the XTAG in the DMA instruction with the real address.
18. The computer program product of claim 16 , wherein the request to initiate the DMA transfer comprises an effective address, and wherein determining, by the adapter, the real address for the DMA transfer using the request comprises translating the effective address to the real address.
19. The computer program product of claim 15 , further comprising computer program instructions that, when executed, cause the adapter to carry out the step of receiving a request to initiate a DMA transfer via a coherency interface, and wherein the DMA instruction comprising the XTAG is received via a DMA interface.
20. The computer program product of claim 19 , wherein the coherency interface is part of a coherency service layer on the adapter, and wherein the DMA interface is part of a DMA layer on the adapter.