IP Library Granted Patent US 10,672,626
Granted Patent B2
US 10,672,626 · App. 15/469,284 · Granted Jun 2, 2020

Method and materials for warpage thermal and interconnect solutions

Inventors: Omkar G. Karhade (Chandler, AZ); Nitin A. Deshpande (Chandler, AZ); Aditya S. Vaidya (Tempe, AZ); Nachiket R. Raravikar (Gilbert, AZ); Eric J. Li (Chandler, AZ)
Assignee: Intel Corporation
H01L21/565H01L21/561H01L21/76879H01L21/76883H01L21/78H01L23/49811H01L24/92H01L25/0657H01L25/105H01L25/50H01L23/3121H01L24/13H01L24/16H01L24/29H01L24/32H01L24/48H01L24/81H01L24/83H01L2224/131H01L2224/16227H01L2224/2919H01L2224/32145H01L2224/32227H01L2224/48227H01L2224/73204H01L2224/73265H01L2224/81203H01L2224/81815H01L2224/83104H01L2224/83203H01L2224/83815H01L2224/92H01L2225/0651H01L2225/06562H01L2924/00014H01L2924/014H01L2924/12042H01L2924/15311H01L2924/181H01L2924/3511
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Quick Facts
Patent No.
US 10,672,626
App. No.
15/469,284
Granted
Jun 2, 2020
Kind
B2
Abstract

Embodiments describe a semiconductor package that includes a substrate, a die bonded to the substrate, and a solder paste overmold layer formed over a top surface of the die. In an embodiment, the solder paste comprises a high-melting point metal, a solder matrix, intermetallic compounds and a polymer. The overmold layer has a high elastic modulus, a coefficient of thermal expansion similar to the substrate, and reduces the warpage of the package. In an embodiment, interconnects of a semiconductor package are formed with a no-slump solder paste that includes vents. Vents may be formed through a conductive network formed by the high-melting point metal, solder matrix and intermetallic compounds. In an embodiment, vents provide a path through the interconnect that allows for moisture outgassing. In an embodiment, a mold layer may be mechanically anchored to the interconnects by the vents, thereby providing improved mechanical continuity to the mold layer.

Claims (11)

1. A method of forming a semiconductor package comprising:

bonding a die to a substrate;

forming an overmold layer over a top surface of the die, wherein the overmold layer is a solder paste comprising a high-melting point metal, a solder matrix, and a polymer;

forming a plurality of interconnects having an aspect ratio greater than 2:1 on a peripheral region around the die with the solder paste; and

curing the solder paste.

2. The method of claim 1 , wherein curing the solder paste comprises a liquid phase sintering process.

3. The method of claim 1 , wherein the high-melting point metal includes copper particles and the solder matrix is a SnBi solder.

4. The method of claim 1 , wherein the polymer has a molecular weight less than approximately 2,000 Da.

5. The method of claim 1 , wherein the overmold layer is printed over the top surface of the die with a stencil printing process.

6. The method of claim 5 , wherein the overmold layer is printed over the top surface of the die before the die is singulated from a wafer comprising a plurality of dies.

7. The semiconductor package of claim 1 , wherein a mold layer is mechanically anchored to the one or more interconnects by vents, wherein the vents provide mechanical anchoring points for the mold layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2025
From: INTEL CORPORATION
To: SK HYNIX NAND PRODUCT SOLUTIONS CORP. (DBA SOLIDIGM)
Reel/Frame 072890/0340 →
Continuity (2)
Division 14229788 · Mar 28, 2014
Related Publication 20170200621A1 · Jul 13, 2017
Cited By (1)
US 12,334,405