IP Library Granted Patent US 10,424,920
Granted Patent B2
US 10,424,920 · App. 15/469,450 · Granted Sep 24, 2019

Semiconductor device

Inventor: Yasuyuki Morishita (Kodaira, JP)
Assignee: RENESAS ELECTRONICS CORPORATION
H02H9/044H01L27/0266
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Quick Facts
Patent No.
US 10,424,920
App. No.
15/469,450
Granted
Sep 24, 2019
Kind
B2
Abstract

A semiconductor device that can have both noise resistance and ESD resistance is provided. The semiconductor device includes a first and a second digital circuits, a first and a second ground potential lines respectively provided corresponding to the first and the second digital circuits, a first and a second analog circuits, a third and a fourth ground potential lines respectively provided corresponding to the first and the second analog circuits, a first bidirectional diode group provided between the first and the second ground potential lines, a second bidirectional diode group provided between the third and the fourth ground potential lines, and a third bidirectional diode group provided between the first and the third ground potential lines. The number of stages of bidirectional diodes of the third bidirectional diode group is greater than that included in each of the first and the second bidirectional diode groups.

Claims (23)

1. A semiconductor device comprising:

a first and a second digital circuits;

a first and a second ground potential lines respectively provided corresponding to the first and the second digital circuits;

a first and a second analog circuits;

a third and a fourth ground potential lines respectively provided corresponding to the first and the second analog circuits;

a first bidirectional diode group provided between the first ground potential line and the second ground potential line;

a second bidirectional diode group provided between the third ground potential line and the fourth ground potential line; and

a third bidirectional diode group provided between the first ground potential line and the third ground potential line,

wherein a number of stages of bidirectional diodes of the third bidirectional diode group is greater than a number of stages of bidirectional diodes included in each of the first and the second bidirectional diode groups,

wherein the first analog circuit further includes a first transistor element including an input gate, and a first clamp element provided between the input gate and the third ground potential line,

wherein the second analog circuit further includes a second transistor element including an input gate, and a second clamp element provided between the input gate and the fourth ground potential line, and

wherein a size of the first clamp element is greater than that of the second clamp element.

2. The semiconductor device according to claim 1 ,

wherein the first and the second bidirectional diode groups are formed by one stage and the third bidirectional diode group is formed by two or more stages.

3. The semiconductor device according to claim 1 ,

wherein the first bidirectional diode group is provided between a digital core area where the first digital circuit is provided and a digital input/output area where the second digital circuit is provided,

wherein the second bidirectional diode group is provided between an analog core area where the first analog circuit is provided and an analog input/output area where the second digital circuit is provided, and

wherein the third bidirectional diode group is provided between the digital core area and the analog core area.

4. The semiconductor device according to claim 3 , further comprising:

a fourth bidirectional diode group which is provided between the second ground potential line and the fourth ground potential line and which has stages of bidirectional diodes, the number of which is greater than the number of stages of bidirectional diodes included in each of the first and the second bidirectional diode groups,

wherein the fourth bidirectional diode group is provided between the digital input/output area and the analog input/output area.

5. The semiconductor device according to claim 1 ,

wherein the first clamp element is coupled between the input gate and the third ground potential line, and a gate of the first clamp element is formed by an N-channel MOS transistor coupled with the third ground potential line.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2017
From: MORISHITA, YASUYUKI
To: RENESAS ELECTRONICS CORPORATION
Reel/Frame 041839/0810 →
Priority Claims (1)
JP 2016-094296 · May 10, 2016 · national
Continuity (1)
Related Publication 20170331284A1 · Nov 16, 2017