Semiconductor device having an electrostatic protection element
View Patent ↗In a semiconductor device that uses an N-channel MOS transistor as an electrostatic protection element, the N-channel MOS transistor has a plurality of electric field relaxing areas, three of which have in a longitudinal direction three different impurity concentrations decreasing from an N-type high concentration drain region downward, and three of which have in a lateral direction three different impurity concentrations decreasing from the N-type high concentration drain region toward a channel region. An electric field relaxing area that is in contact with the electric field relaxing areas in the longitudinal direction and with the electric field relaxing areas in the lateral direction has the lowest impurity concentration.
1. A semiconductor device comprising an N-channel MOS transistor, the N-channel MOS transistor comprising:
a field oxide film and a gate oxide film on a semiconductor substrate;
a gate electrode on the gate oxide film, the gate electrode having a first end extending to the field oxide film;
an N-type high concentration source region at a second end of the gate electrode;
a channel region under the gate oxide film and sandwiched between the N-type high concentration source region and a first end portion of the field oxide film;
an N-type high concentration drain region at a second end portion of the field oxide film opposite from the first end portion of the field oxide film; and
a plurality of electric field relaxing areas under the field oxide film, and around the N-type high concentration drain region, the plurality of electric field relaxing areas comprising:
first electric field relaxing areas each extending in a longitudinal direction, such that three different impurity concentration regions decrease in concentration from the N-type high concentration drain region downward,
second electric field relaxing areas each extending in a lateral direction, such that three different impurity regions decrease in concentration from the N-type high concentration drain region toward the channel region, and
a third electric field relaxing area contacting the electric field relaxing areas in the longitudinal direction and the electric field relaxing areas in the lateral direction and displaced from the channel region by an intermediate one of the second electric field relaxing areas, and having a lowest in impurity concentration among the plurality of electric field relaxing areas,
wherein the intermediate one and an adjacent one of the second electric field relaxing areas and the third electric field relaxing area reside in a P-type well region.
2. A semiconductor device comprising an N-channel MOS transistor, the N-channel MOS transistor comprising:
a field oxide film and a gate oxide film on a semiconductor substrate;
a gate electrode on the gate oxide film, the gate electrode having a first end extending to the field oxide film;
an N-type high concentration source region at a second end of the gate electrode;
a channel region under the gate oxide film and sandwiched between the N-type high concentration source region and a first end portion of the field oxide film;
an N-type high concentration drain region at a second end portion of the field oxide film opposite from the first end portion of the field oxide film; and
a plurality of electric field relaxing areas under the field oxide film, and around the N-type high concentration drain region, the plurality of electric field relaxing areas comprising:
electric field relaxing areas extending in a longitudinal direction, such that three different impurity concentration regions decrease in concentration from the N-type high concentration drain region downward,
electric field relaxing areas each extending in a lateral direction, such that three different impurity regions decrease in concentration from the N-type high concentration drain region toward the channel region, and
an electric field relaxing area contacting the electric field relaxing areas in the longitudinal direction and the electric field relaxing areas in the lateral direction, and having a lowest in impurity concentration among the plurality of electric field relaxing areas,
wherein the plurality of electric field relaxing areas comprise regions where an N-type intermediate concentration diffusion region overlaps with a P-type well region, with a first N-type well region, and with a second N-type well region.
3. A semiconductor device according to claim 2 , wherein the first N-type well region has a depth in the semiconductor substrate that is deeper than a depth of the second N-type well region, and the depth in the semiconductor substrate of the second N-type well region is deeper than a depth of the N-type intermediate concentration diffusion region.
4. A semiconductor device according to claim 2 , wherein the second N-type well region does not overlap the first end of the gate electrode that extends to the top of the field oxide film.