System and method for an ovenized silicon platform using Si/SiO

1. An ovenized silicon platform comprising:

at least one silicon layer;

at least one silicon oxide layer;

a hybrid Si/SiO 2 platform support structure,

wherein said support structure is formed by depositing silicon oxide within trenches formed by a deep reactive ion etching of a silicon layer to create alternating layers of silicon and silicon oxide configured to thermally isolate the platform from temperature fluctuations; and

at least one thin-film electrical interconnect displaced on the top surface of said platform.

2. The platform of claim 1 further comprising: at least one element selected from the group comprising CMOS circuitry, thermal sensor, heater, and inertial sensor.

3. The platform of claim 1 wherein the alternating layers of silicon and silicon oxide within the platform support structure are separated by a layer of silicon nitride.

4. The platform of claim 1 wherein the at least one silicon layer is a device layer of a silicon-on-isolator wafer.

5. The platform of claim 2 comprising at least one thermal sensor and at least one heater wherein said at least one thermal sensor and said at least one heater are each positioned within a layer of silicon.

6. The platform of claim 2 comprising at least one thermal sensor and at least one heater wherein said at least one thermal sensor and said at least one heater are each positioned on the top surface of said platform.

7. The platform of claim 1 wherein the thin-film electrical interconnect is a trace comprising metal or polysilicon.

8. A method for fabricating an ovenized silicon platform, said method comprising the steps of:

deep-reactive-ion-etching trenches into a layer of silicon on one side of said platform;

forming a recess on a side of the platform opposite to that of said trenches;

depositing a layer of oxide onto a top layer of the platform to refill said trenches

thereby having a patterned platform support structure of alternating layers of silicon and silicon oxide that provides thermal isolation for the platform;

attaching conductive traces onto a surface of the platform; and

releasing said support structure.

9. The method of claim 8 further comprising the step of:

integrating CMOS circuitry with the platform.

10. The method of claim 8 further comprising the steps of:

depositing a first layer of nitride onto a layer of silicon prior to depositing a layer of oxide on a top layer of the platform; and

then depositing a second layer of nitride onto the layer of oxide to create a layer of oxide sandwiched between layers of nitride deposited on a top surface of the platform.

11. The method of claim 10 further comprising the steps of:

patterning the silicon oxide layer to create depressions therein; and

encapsulating said depressions with nitride during the deposition of the second layer of nitride to create lateral etch stops.

12. The method of claim 8 further comprising the steps of:

defining at least one inertial sensor along with said trenches during the deep-reactive-ion-etching step;

releasing said at least one inertial sensor;

fitting a sensor cap over said at least one inertial sensor;

fitting a top cap on a top surface of said platform; and

fitting a bottom cap on a bottom surface of said platform.

13. The method of claim 12 further comprising the step of:

integrating CMOS circuitry with the platform.

14. The method of claim 8 further comprising the steps of:

attaching at least one of an unpackaged sensor or a packaged sensor to a top surface of the platform;

attaching said platform within an electronic chip package; and

covering said package with a lid.

15. The method of claim 14 further comprising the steps of:

vacuum sealing said ceramic package.

16. The method of claim 14 where in the sensor attachment step is accomplished by either flip-chip bonding, eutectic bonding, or wirebond connection.

17. The method of claim 14 wherein the electronic chip package is ceramic.

18. The method of claim 14 further comprising the step of:

integrating CMOS circuitry with the platform.

19. The method of claim 15 further comprising the step of:

integrating CMOS circuitry with the platform.

20. The method of claim 16 further comprising the step of:

integrating CMOS circuitry with the platform.